diff options
| author | Greg Watson <jarrah@users.sourceforge.net> | 2004-06-05 14:36:23 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2004-06-05 14:36:23 +0000 |
| commit | 8ce104f487a8248be143b4436b7a4abc3969bb6f (patch) | |
| tree | 25b52793e9be2be4b78a666f29e1d44e45722714 /src/northbridge/ibm/cpc710/cpc710.h | |
| parent | 2f2e63bc7dd27b526d300a7aa712a0af4ec85e3e (diff) | |
memory and pci up!
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/ibm/cpc710/cpc710.h')
| -rw-r--r-- | src/northbridge/ibm/cpc710/cpc710.h | 25 |
1 files changed, 1 insertions, 24 deletions
diff --git a/src/northbridge/ibm/cpc710/cpc710.h b/src/northbridge/ibm/cpc710/cpc710.h index f43a851cf2..7c5a37bb5c 100644 --- a/src/northbridge/ibm/cpc710/cpc710.h +++ b/src/northbridge/ibm/cpc710/cpc710.h @@ -81,35 +81,12 @@ #define CPC710_SDRAM0_SIOR0 0x1400 #define CPC710_SDRAM0_SIOR1 0x1420 -#define CPC710_BRIDGE_PSEA 0xf6110 -#define CPC710_BRIDGE_PCIDG 0xf6120 -#define CPC710_BRIDGE_INTACK 0xf7700 -#define CPC710_BRIDGE_PIBAR 0xf7800 -#define CPC710_BRIDGE_PMBAR 0xf7810 -#define CPC710_BRIDGE_CRR 0xf7ef0 -#define CPC710_BRIDGE_PR 0xf7f20 -#define CPC710_BRIDGE_ACR 0xf7f30 -#define CPC710_BRIDGE_MSIZE 0xf7f40 -#define CPC710_BRIDGE_IOSIZE 0xf7f60 -#define CPC710_BRIDGE_SMBAR 0xf7f80 -#define CPC710_BRIDGE_SIBAR 0xf7fc0 -#define CPC710_BRIDGE_CTLRW 0xf7fd0 -#define CPC710_BRIDGE_CFGADDR 0xf8000 -#define CPC710_BRIDGE_CFGDATA 0xf8010 -#define CPC710_BRIDGE_PSSIZE 0xf8100 -#define CPC710_BRIDGE_BARPS 0xf8120 -#define CPC710_BRIDGE_PSBAR 0xf8140 -#define CPC710_BRIDGE_BPMDLK 0xf8200 -#define CPC710_BRIDGE_TPMDLK 0xf8210 -#define CPC710_BRIDGE_BIODLK 0xf8220 -#define CPC710_BRIDGE_TIODLK 0xf8230 -#define CPC710_BRIDGE_INTSET 0xf8310 - /* Configuration space registers */ #define CPC710_BUS_NUMBER 0x40 #define CPC710_SUB_BUS_NUMBER 0x41 /* MCCR register bits */ +#define CPC710_MCCR_INIT_STATUS 0x20000000 #define CPC710_MCCR_DIAG_MODE 0x40000000 #define CPC710_MCCR_ECC_DISABLE 0x08000000 #define CPC710_MCCR_REFRESH_7CY 0x02000000 |