diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2015-01-05 12:59:54 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-01-06 20:15:02 +0100 |
| commit | 65b72ab55d7dff1f13cdf495d345e04e634b97ac (patch) | |
| tree | 11771914bc4459d7cf9e020ff4489e9bb6a81e75 /src/northbridge/dmp | |
| parent | d42c9dae8528594b2ab8534d061c118c15e92d3d (diff) | |
northbridge: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the northbridge code to use printk() on all non-ROMCC
boards.
Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7856
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/dmp')
| -rw-r--r-- | src/northbridge/dmp/vortex86ex/raminit.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/dmp/vortex86ex/raminit.c b/src/northbridge/dmp/vortex86ex/raminit.c index 2382fe2440..227b376a7e 100644 --- a/src/northbridge/dmp/vortex86ex/raminit.c +++ b/src/northbridge/dmp/vortex86ex/raminit.c @@ -258,17 +258,17 @@ static u8 detect_ddr3_dram_size(void) static void print_ddr3_memory_setup(void) { #if CONFIG_DEBUG_RAM_SETUP - print_debug("DDR3 Timing Reg 0-3:\n"); - print_debug("NB 6e : "); + printk(BIOS_DEBUG, "DDR3 Timing Reg 0-3:\n"); + printk(BIOS_DEBUG, "NB 6e : "); print_debug_hex16(pci_read_config16(NB, 0x6e)); - print_debug("\nNB 74 : "); + printk(BIOS_DEBUG, "\nNB 74 : "); print_debug_hex32(pci_read_config32(NB, 0x74)); - print_debug("\nNB 78 : "); + printk(BIOS_DEBUG, "\nNB 78 : "); print_debug_hex32(pci_read_config32(NB, 0x78)); - print_debug("\nNB 7c : "); + printk(BIOS_DEBUG, "\nNB 7c : "); print_debug_hex32(pci_read_config32(NB, 0x7c)); u16 mbr = pci_read_config16(NB, 0x6c); - print_debug("\nNB 6c(MBR) : "); + printk(BIOS_DEBUG, "\nNB 6c(MBR) : "); print_debug_hex16(mbr); const char *s; u8 col = get_ddr3_mem_reg_col(mbr); |