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authorLi-Ta Lo <ollie@lanl.gov>2004-03-23 21:28:05 +0000
committerLi-Ta Lo <ollie@lanl.gov>2004-03-23 21:28:05 +0000
commite52666931a3e34895b3f3b92641de9774ab722ec (patch)
tree890bb66a0a16ec7a57230283f000ee91eeb0b384 /src/northbridge/amd
parent9f46132e9627d24f3ad76619cf3340006a4012fb (diff)
Doxidization, reformat
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdk8/early_ht.c6
-rw-r--r--src/northbridge/amd/amdk8/northbridge.c54
-rw-r--r--src/northbridge/amd/amdk8/raminit.c2
3 files changed, 49 insertions, 13 deletions
diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index 90f258e1bc..be79545531 100644
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -16,8 +16,8 @@ static int enumerate_ht_chain(void)
id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
/* If the chain is enumerated quit */
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
break;
}
hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
@@ -25,7 +25,7 @@ static int enumerate_ht_chain(void)
hdr_type &= 0x7f;
if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
- (hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
+ (hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
}
while(pos != 0) {
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 12d8f73c0b..d63f416717 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -42,7 +42,7 @@ struct mem_range *sizeram(void)
printk_debug("mmio_base: %dKB\n", mmio_basek);
#endif
- for(idx = i = 0; i < 8; i++) {
+ for (idx = i = 0; i < 8; i++) {
uint32_t base, limit;
unsigned basek, limitk, sizek;
base = pci_read_config32(dev, 0x40 + (i<<3));
@@ -54,18 +54,18 @@ struct mem_range *sizeram(void)
limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
sizek = limitk - basek;
if ((idx > 0) &&
- ((mem[idx -1].basek + mem[idx - 1].sizek) == basek)) {
+ ((mem[idx - 1].basek + mem[idx - 1].sizek) == basek)) {
mem[idx -1].sizek += sizek;
- }
- else {
+ } else {
mem[idx].basek = basek;
mem[idx].sizek = sizek;
idx++;
}
/* see if we need a hole from 0xa0000 to 0xbffff */
- if((mem[idx-1].basek < ((8*64)+(8*16))) &&
- (mem[idx-1].sizek > ((8*64)+(16*16)))) {
+ if ((mem[idx-1].basek < ((8*64)+(8*16))) /* 640 */ &&
+ (mem[idx-1].sizek > ((8*64)+(16*16))) /* 768 */ ) {
+#warning "FIXME: this left 0xA0000 to 0xBFFFF undefined"
mem[idx].basek = (8*64)+(16*16);
mem[idx].sizek = mem[idx-1].sizek - ((8*64)+(16*16));
mem[idx-1].sizek = ((8*64)+(8*16)) - mem[idx-1].basek;
@@ -74,7 +74,7 @@ struct mem_range *sizeram(void)
/* See if I need to split the region to accomodate pci memory space */
if ((mem[idx - 1].basek <= mmio_basek) &&
- ((mem[idx - 1].basek + mem[idx - 1].sizek) > mmio_basek)) {
+ ((mem[idx - 1].basek + mem[idx - 1].sizek) > mmio_basek)) {
if (mem[idx - 1].basek < mmio_basek) {
unsigned pre_sizek;
pre_sizek = mmio_basek - mem[idx - 1].basek;
@@ -92,10 +92,10 @@ struct mem_range *sizeram(void)
}
}
}
-#if 0
- for(i = 0; i < idx; i++) {
+#if 1
+ for (i = 0; i < idx; i++) {
printk_debug("mem[%d].basek = %08x mem[%d].sizek = %08x\n",
- i, mem[i].basek, i, mem[i].sizek);
+ i, mem[i].basek, i, mem[i].sizek);
}
#endif
while(idx < sizeof(mem)/sizeof(mem[0])) {
@@ -514,6 +514,40 @@ static void mcf0_control_init(struct device *dev)
printk_debug("done.\n");
}
+
+static void amdk8_enable_resources(struct device *dev)
+{
+ uint16_t ctrl;
+ unsigned link;
+ unsigned int vgalink = -1;
+
+ ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ ctrl |= dev->link[0].bridge_ctrl;
+ printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+ printk_err("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
+
+#if 0
+ /* let's see what link VGA is on */
+ for(link = 0; link < dev->links; link++) {
+ device_t child;
+ printk_err("Kid %d of k8: bridge ctrl says: 0x%x\n",
+ link, dev->link[link].bridge_ctrl);
+ if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
+ vgalink = link;
+ }
+
+ if (vgalink != 1) {
+ /* now find the IOPAIR that goes to vgalink and set the vga enable in the base part (0x30) */
+ /* now allocate an MMIOPAIR and point it to the CPU0, LINK=vgalink */
+ /* now set IORR1 so it has a hole for the 0xa0000-0xcffff region */
+ }
+#endif
+
+ pci_dev_enable_resources(dev);
+ //enable_childrens_resources(dev);
+}
+
static struct device_operations northbridge_operations = {
.read_resources = amdk8_read_resources,
.set_resources = amdk8_set_resources,
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index e5bcb2d02f..fac24d7beb 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -5,10 +5,12 @@
#if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
# error "CONFIG_LB_MEM_TOPK must be a power of 2"
#endif
+
static void setup_resource_map(const unsigned int *register_values, int max)
{
int i;
print_debug("setting up resource map....");
+
#if 0
print_debug("\r\n");
#endif