summaryrefslogtreecommitdiff
path: root/src/northbridge/amd
diff options
context:
space:
mode:
authorEric Biederman <ebiederm@xmission.com>2003-07-19 04:28:22 +0000
committerEric Biederman <ebiederm@xmission.com>2003-07-19 04:28:22 +0000
commit9b4336cf418d22551bea09d93e1cee79281b110e (patch)
tree3f1e24216c11918644a98fd1e46e2fdb40fd12fe /src/northbridge/amd
parentfe4414587a4466b848184b8837d4c5a280949824 (diff)
- Major cleanup of the bootpath
- Changes to allow more code to be compiled both ways - Working SMP support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdk8/coherent_ht.c21
-rw-r--r--src/northbridge/amd/amdk8/early_ht.c6
-rw-r--r--src/northbridge/amd/amdk8/raminit.c2
-rw-r--r--src/northbridge/amd/amdk8/reset_test.c43
4 files changed, 57 insertions, 15 deletions
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 460284bc82..23ebd60e81 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -440,13 +440,7 @@ static void enable_routing(u8 node)
print_debug_hex32(node);
val=pci_read_config32(NODE_HT(node), 0x6c);
- val |= (1 << 6) | (1 << 5) | (1 << 4);
-#if 0
val &= ~((1<<1)|(1<<0));
-#else
- /* Don't enable requests here as the indicated processor starts booting */
- val &= ~(1<<0);
-#endif
pci_write_config32(NODE_HT(node), 0x6c, val);
print_debug(" done.\r\n");
@@ -456,7 +450,7 @@ static void enable_routing(u8 node)
static void rename_temp_node(u8 node)
{
- u32 val;
+ uint32_t val;
print_debug("Renaming current temp node to ");
print_debug_hex32(node);
@@ -678,8 +672,8 @@ static u8 setup_smp(void)
/* We found 2 nodes so far */
setup_node(0, cpus); /* Node 1 is there. Setup Node 0 correctly */
setup_remote_node(1, cpus); /* Setup the routes on the remote node */
- enable_routing(7); /* Enable routing on Node 1 */
rename_temp_node(1); /* Rename Node 7 to Node 1 */
+ enable_routing(1); /* Enable routing on Node 1 */
clear_temp_row(0); /* delete temporary connection */
@@ -716,14 +710,14 @@ static u8 setup_smp(void)
setup_temp_row(0,2,cpus);
setup_temp_node(2,cpus);
- enable_routing(7);
rename_temp_node(2);
+ enable_routing(2);
setup_temp_row(0,1,cpus);
setup_temp_row(1,3,cpus);
setup_temp_node(3,cpus);
- enable_routing(7); /* enable routing on node 3 (temp.) */
rename_temp_node(3);
+ enable_routing(3); /* enable routing on node 3 (temp.) */
clear_temp_row(0);
clear_temp_row(1);
@@ -820,13 +814,14 @@ static void coherent_ht_finalize(unsigned cpus)
}
#if 1
- print_debug("done\n");
+ print_debug("done\r\n");
#endif
}
-static void setup_coherent_ht_domain(void)
+static int setup_coherent_ht_domain(void)
{
unsigned cpus;
+ int reset_needed = 0;
enable_bsp_routing();
@@ -837,6 +832,8 @@ static void setup_coherent_ht_domain(void)
cpus=detect_mp_capabilities(cpus);
#endif
coherent_ht_finalize(cpus);
+
+ return reset_needed;
}
#endif
diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index b8262d519c..4de8fa1075 100644
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -1,11 +1,12 @@
-static void enumerate_ht_chain(void)
+static int enumerate_ht_chain(unsigned link)
{
/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
* On most boards this just happens. If a cpu has multiple
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/
- unsigned next_unitid, last_unitid;;
+ unsigned next_unitid, last_unitid;
+ int reset_needed = 0;
next_unitid = 1;
do {
uint32_t id;
@@ -46,4 +47,5 @@ static void enumerate_ht_chain(void)
pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
}
} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
+ return reset_needed;
}
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index fd5956743f..41a93b51e9 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -1135,7 +1135,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
pci_write_config32(ctrl->f1, 0x44, limit | (0 << 8) | (node_id << 0));
pci_write_config32(ctrl->f1, 0x40, base | (0 << 8) | (1<<1) | (1<<0));
-#if 0
+#if 1
pci_write_config32(PCI_DEV(0, 0x19, 1), 0x44, limit | (0 << 8) | (1 << 4) | (node_id << 0));
pci_write_config32(PCI_DEV(0, 0x19, 1), 0x40, base | (0 << 8) | (1<<1) | (1<<0));
#endif
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
new file mode 100644
index 0000000000..949bd7cc15
--- /dev/null
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -0,0 +1,43 @@
+#include <stdint.h>
+#define NODE_ID 0x60
+#define HT_INIT_CONTROL 0x6c
+
+#define HTIC_ColdR_Detect (1<<4)
+#define HTIC_BIOSR_Detect (1<<5)
+#define HTIC_INIT_Detect (1<<6)
+
+
+static int cpu_init_detected(void)
+{
+ unsigned long dcl;
+ int cpu_init;
+
+ unsigned long htic;
+
+ htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+#if 0
+ print_debug("htic: ");
+ print_debug_hex32(htic);
+ print_debug("\r\n");
+
+ if (!(htic & HTIC_ColdR_Detect)) {
+ print_debug("Cold Reset.\r\n");
+ }
+ if ((htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect)) {
+ print_debug("BIOS generated Reset.\r\n");
+ }
+ if (htic & HTIC_INIT_Detect) {
+ print_debug("Init event.\r\n");
+ }
+#endif
+ cpu_init = (htic & HTIC_INIT_Detect);
+ return cpu_init;
+}
+
+static void distinguish_cpu_resets(void)
+{
+ uint32_t htic;
+ htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+ htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
+ pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+}