printk_foo -> printk(BIOS_FOO, ...)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

33 files changed, 366 insertions, 367 deletions

diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 826037194d..1fbef83236 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1134,7 +1134,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 #ifdef __PRE_RAM__
 		print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
 #else
-		printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
+		printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
 #endif
 		switch(sysinfo->mem_trained[i]) {
 		case 0: //don't need train
@@ -1152,7 +1152,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 		print_debug("mem trained failed\n");
 		soft_reset();
 #else
-		printk_debug("mem trained failed\n");
+		printk(BIOS_DEBUG, "mem trained failed\n");
 		hard_reset();
 #endif
 	}
diff --git a/src/northbridge/amd/amdfam10/amdfam10_acpi.c b/src/northbridge/amd/amdfam10/amdfam10_acpi.c
index 0d31c2eb02..0a35861556 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_acpi.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_acpi.c
@@ -60,7 +60,7 @@ unsigned long acpi_create_srat_lapics(unsigned long current)
 		if (!cpu->enabled) {
 			continue;
 		}
-		printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
+		printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		cpu_index++;
 	}
@@ -89,7 +89,7 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
 	basek = resk(res->base);
 	sizek = resk(res->size);
 
-	printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
+	printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
 			dev_path(dev), res->index, basek, sizek);
 	/*
 	 * 0-640K must be on node 0
@@ -338,7 +338,7 @@ unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current)
 		if (!cpu->enabled) {
 			 continue;
 		}
-		printk_debug("ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.core_id);
+		printk(BIOS_DEBUG, "ACPI: pstate cpu_index=%02x, node_id=%02x, core_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.core_id);
 
 		current	  = ( current + 0x0f) & -0x10;
 		ssdt = (acpi_header_t *)current;
diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c
index b52bedad7b..df578044a6 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_conf.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c
@@ -779,7 +779,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
 #if 0
 		// FIXME: can we use VGA reg instead?
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-			printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
+			printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
 				__func__, dev_path(dev), link);
 			tempreg |= PCI_IO_BASE_VGA_EN;
 		}
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 7fea9a0483..826b83ac0e 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -28,16 +28,16 @@ static void udelay_tsc(u32 us);
 static  void print_debug_addr(const char *str, void *val)
 {
 #if CACHE_AS_RAM_ADDRESS_DEBUG == 1
-		printk_debug("------Address debug: %s%x------\n", str, val);
+		printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
 #endif
 }
 
 static void print_debug_pci_dev(u32 dev)
 {
 #if CONFIG_PCI_BUS_SEGN_BITS==0
-	printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
+	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 #else
-	printk_debug("PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
+	printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 #endif
 }
 
@@ -55,7 +55,7 @@ static void print_pci_devices(void)
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
+		printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
 		if(((dev>>12) & 0x07) == 0) {
 			u8 hdr_type;
 			hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
@@ -80,7 +80,7 @@ static void print_pci_devices_on_bus(u32 busn)
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
+		printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
 		if(((dev>>12) & 0x07) == 0) {
 			u8 hdr_type;
 			hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
@@ -103,11 +103,11 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
 	for(i = start_reg; i < end; i+=4) {
 		u32 val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("\n%04x:",i);
+			printk(BIOS_DEBUG, "\n%04x:",i);
 		}
 		val = pci_read_config32(dev, i);
 		for(j=0;j<4;j++) {
-			printk_debug(" %02x", val & 0xff);
+			printk(BIOS_DEBUG, " %02x", val & 0xff);
 			val >>= 8;
 		}
 	}
@@ -129,10 +129,10 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
 	for(i = start; i < end; i++) {
 		u32 val;
 		int j;
-		printk_debug("\n%02x:",i);
+		printk(BIOS_DEBUG, "\n%02x:",i);
 		val = pci_read_config32_index_wait(dev, index_reg, i);
 		for(j=0;j<4;j++) {
-			printk_debug(" %02x", val & 0xff);
+			printk(BIOS_DEBUG, " %02x", val & 0xff);
 			val >>= 8;
 		}
 
@@ -160,10 +160,10 @@ static void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
 	for(i = 0; i < length; i++) {
 		u32 val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("\n%02x:",i);
+			printk(BIOS_DEBUG, "\n%02x:",i);
 		}
 		val = pci_read_config32_index(dev, index_reg, i|type);
-		printk_debug(" %08x", val);
+		printk(BIOS_DEBUG, " %08x", val);
 	}
 	print_debug("\n");
 }
@@ -231,38 +231,38 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
 		device = ctrl->spd_addr[i];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.0: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				u8 byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
 		device = ctrl->spd_addr[i+DIMM_SOCKETS];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.1: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				u8 byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
@@ -275,7 +275,7 @@ static void dump_smbus_registers(void)
 	for(device = 1; device < 0x80; device++) {
 		int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
-		printk_debug("smbus: %02x", device);
+		printk(BIOS_DEBUG, "smbus: %02x", device);
 		for(j = 0; j < 256; j++) {
 			int status;
 			u8 byte;
@@ -284,10 +284,10 @@ static void dump_smbus_registers(void)
 				break;
 			}
 			if ((j & 0xf) == 0) {
-				printk_debug("\n%02x: ",j);
+				printk(BIOS_DEBUG, "\n%02x: ",j);
 			}
 			byte = status & 0xff;
-			printk_debug("%02x ", byte);
+			printk(BIOS_DEBUG, "%02x ", byte);
 		}
 		print_debug("\n");
 	}
@@ -298,14 +298,14 @@ static void dump_io_resources(u32 port)
 
 	int i;
 	udelay_tsc(2000);
-	printk_debug("%04x:\n", port);
+	printk(BIOS_DEBUG, "%04x:\n", port);
 	for(i=0;i<256;i++) {
 		u8 val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("%02x:", i);
+			printk(BIOS_DEBUG, "%02x:", i);
 		}
 		val = inb(port);
-		printk_debug(" %02x",val);
+		printk(BIOS_DEBUG, " %02x",val);
 		if ((i & 0x0f) == 0x0f) {
 			print_debug("\n");
 		}
@@ -319,9 +319,9 @@ static void dump_mem(u32 start, u32 end)
 	print_debug("dump_mem:");
 	for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (u8)*((u8 *)i));
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
 	}
 	print_debug("\n");
 }
diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c
index f6a196aabf..fa2e56065d 100644
--- a/src/northbridge/amd/amdfam10/get_pci1234.c
+++ b/src/northbridge/amd/amdfam10/get_pci1234.c
@@ -75,12 +75,12 @@ void get_pci1234(void)
 	//here we need to set hcdn
 	//1. hypertransport.c need to record hcdn_reg together with 0xe0, 0xe4, 0xe8, 0xec when are set
 	//2. so at the same time we need update hsdn with hcdn_reg here
-//	printk_debug("sysconf.ht_c_num = %02d\n", sysconf.ht_c_num);
+//	printk(BIOS_DEBUG, "sysconf.ht_c_num = %02d\n", sysconf.ht_c_num);
 
 	for(j=0;j<sysconf.ht_c_num;j++) {
 		u32 dwordx;
 		dwordx = sysconf.ht_c_conf_bus[j];
-//		printk_debug("sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]);
+//		printk(BIOS_DEBUG, "sysconf.ht_c_conf_bus[%02d] = %08x\n", j, sysconf.ht_c_conf_bus[j]);
 		dwordx &=0xfffffffd; //keep bus num, node_id, link_num, enable bits
 		if((dwordx & 0x7fd) == dword) { //SBLINK
 			sysconf.pci1234[0] = dwordx;
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index c0650e72f0..472382c9a7 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -125,7 +125,7 @@ static void misc_control_init(struct device *dev)
 {
 	u32 cmd;
 
-	printk_debug("NB: Function 3 Misc Control.. ");
+	printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 
 	/* Disable Machine checks from Invalid Locations.
 	 * This is needed for PC backwards compatibility.
@@ -134,7 +134,7 @@ static void misc_control_init(struct device *dev)
 	cmd |= (1<<6) | (1<<25);
 	pci_write_config32(dev, 0x44, cmd );
 
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 4e1ccd6059..543d74cbfd 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -83,7 +83,7 @@ static void get_fx_devs(void)
 		__f4_dev[i] = get_node_pci(i, 4);
 	}
 	if (!__f1_dev[0]) {
-		printk_err("Cannot find %02x:%02x.1", CONFIG_CBB, CONFIG_CDB);
+		printk(BIOS_ERR, "Cannot find %02x:%02x.1", CONFIG_CBB, CONFIG_CDB);
 		die("Cannot go on\n");
 	}
 }
@@ -568,7 +568,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
 	for (link = 0; link < dev->links; link++) {
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 #if CONFIG_CONSOLE_VGA_MULTI == 1
-			printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
+			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
 				dev->link[link].secondary,dev->link[link].subordinate);
 			/* We need to make sure the vga_pri is under the link */
 			if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
@@ -583,7 +583,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
 	if (link == dev->links)
 		return;
 
-	printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
+	printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
 	set_vga_enable_reg(nodeid, link);
 }
 
@@ -906,9 +906,9 @@ static void pci_domain_set_resources(device_t dev)
 		mem1 = find_resource(dev, 1|(link<<2));
 		mem2 = find_resource(dev, 2|(link<<2));
 
-		printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem1->base, mem1->limit, mem1->size, mem1->align);
-		printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem2->base, mem2->limit, mem2->size, mem2->align);
 
 		/* See if both resources have roughly the same limits */
@@ -934,9 +934,9 @@ static void pci_domain_set_resources(device_t dev)
 			mem1->base = resource_max(mem1);
 		}
 
-		printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem1->base, mem1->limit, mem1->size, mem1->align);
-		printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+		printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 			mem2->base, mem2->limit, mem2->size, mem2->align);
 	}
 
@@ -1041,7 +1041,7 @@ static void pci_domain_set_resources(device_t dev)
 
 		}
 
-//		printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk);
+//		printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk);
 
 		/* split the region to accomodate pci memory space */
 		if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
@@ -1057,7 +1057,7 @@ static void pci_domain_set_resources(device_t dev)
 					/* Leave some space for ACPI, PIRQ and MP tables */
 						high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
 						high_tables_size = HIGH_TABLES_SIZE * 1024;
-						printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
+						printk(BIOS_DEBUG, "(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
 							     high_tables_base);
 					}
 #endif
@@ -1086,7 +1086,7 @@ static void pci_domain_set_resources(device_t dev)
 		ram_resource(dev, (idx | i), basek, sizek);
 		idx += 0x10;
 #if CONFIG_WRITE_HIGH_TABLES==1
-		printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
+		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
 			     i, mmio_basek, basek, limitk);
 		if (i==0 && high_tables_base==0) {
 		/* Leave some space for ACPI, PIRQ and MP tables */
@@ -1144,7 +1144,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
 			if (!dev->link[0].disable_relaxed_ordering) {
 				httc |= HTTC_RSP_PASS_PW;
 			}
-			printk_spew("%s passpw: %s\n",
+			printk(BIOS_SPEW, "%s passpw: %s\n",
 				dev_path(dev),
 				(!dev->link[0].disable_relaxed_ordering)?
 				"enabled":"disabled");
@@ -1247,34 +1247,34 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 #if CONFIG_CBB
 	dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
 	if(dev_mc && dev_mc->bus) {
-		printk_debug("%s found", dev_path(dev_mc));
+		printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
 		pci_domain = dev_mc->bus->dev;
 		if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
-			printk_debug("\n%s move to ",dev_path(dev_mc));
+			printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
 			dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
-			printk_debug("%s",dev_path(dev_mc));
+			printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
 
 		} else {
-			printk_debug(" but it is not under pci_domain directly ");
+			printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
 		}
-		printk_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 
 	}
 	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
 	if(!dev_mc) {
 		dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 		if (dev_mc && dev_mc->bus) {
-			printk_debug("%s found\n", dev_path(dev_mc));
+			printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
 			pci_domain = dev_mc->bus->dev;
 			if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
 				if((pci_domain->links==1) && (pci_domain->link[0].children == dev_mc)) {
-					printk_debug("%s move to ",dev_path(dev_mc));
+					printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
 					dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
-					printk_debug("%s\n",dev_path(dev_mc));
+					printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
 					while(dev_mc){
-						printk_debug("%s move to ",dev_path(dev_mc));
+						printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
 						dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
-						printk_debug("%s\n",dev_path(dev_mc));
+						printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
 						dev_mc = dev_mc->sibling;
 					}
 				}
@@ -1286,7 +1286,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 
 	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
 	if (!dev_mc) {
-		printk_err("%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
+		printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
 		die("");
 	}
 
@@ -1301,7 +1301,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 			pci_domain->link[1].link = 1;
 			pci_domain->link[1].dev = pci_domain;
 			pci_domain->link[1].children = 0;
-			printk_debug("%s links increase to %d\n", dev_path(pci_domain), pci_domain->links);
+			printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(pci_domain), pci_domain->links);
 		}
 		pci_domain->link[1].secondary = CONFIG_CBB - 1;
 	}
@@ -1355,7 +1355,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 					 dev->link[j].dev = dev;
 				}
 				dev->links = linknum;
-				printk_debug("%s links increase to %d\n", dev_path(dev), dev->links);
+				printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(dev), dev->links);
 			}
 		}
 
@@ -1366,7 +1366,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 			cores_found = (j >> 12) & 3; // dev is func 3
 			if (siblings > 3)
 				cores_found |= (j >> 13) & 4;
-			printk_debug("  %s siblings=%d\n", dev_path(dev), cores_found);
+			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(dev), cores_found);
 		}
 
 		u32 jj;
@@ -1416,7 +1416,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 					 }
 				}
 	#endif
-				printk_debug("CPU: %s %s\n",
+				printk(BIOS_DEBUG, "CPU: %s %s\n",
 					dev_path(cpu), cpu->enabled?"enabled":"disabled");
 			}
 
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 21f1e188e5..4b33fd6f86 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -20,7 +20,7 @@
 
 static  void print_raminit(const char *strval, u32 val)
 {
-	printk_debug("%s%08x\n", strval, val);
+	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
 }
 
 static  void print_tx(const char *strval, u32 val)
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c
index b91c9222c1..0d6d743750 100644
--- a/src/northbridge/amd/amdfam10/setup_resource_map.c
+++ b/src/northbridge/amd/amdfam10/setup_resource_map.c
@@ -81,7 +81,7 @@ static void setup_resource_map_x_offset(const u32 *register_values, u32 max,
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
 			i/4, register_values[i],
 			register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
 			register_values[i+2],
@@ -146,7 +146,7 @@ static void setup_resource_map_x(const u32 *register_values, u32 max)
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
 		i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
 #endif
 		switch (register_values[i]) {
diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c
index 249388b04a..4f735645f8 100644
--- a/src/northbridge/amd/amdht/comlib.c
+++ b/src/northbridge/amd/amdht/comlib.c
@@ -240,7 +240,7 @@ void CALLCONV AmdMSRWrite(uint32 Address, uint64 *Value)
 
 void ErrorStop(u32 value)
 {
-	printk_debug("Error: %08x ", value);
+	printk(BIOS_DEBUG, "Error: %08x ", value);
 
 }
 
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index 678ba6ce9a..a2b4076d22 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -84,13 +84,13 @@ void AMD_CB_EventNotify (u8 evtClass, u16 event, u8 *pEventData0)
 {
 	u8 i;
 
-	printk_debug("AMD_CB_EventNotify()\n");
-	printk_debug(" event class: %02x\n event: %04x\n data: ", evtClass, event);
+	printk(BIOS_DEBUG, "AMD_CB_EventNotify()\n");
+	printk(BIOS_DEBUG, " event class: %02x\n event: %04x\n data: ", evtClass, event);
 
 	for (i = 0; i < *pEventData0; i++) {
-		printk_debug(" %02x ", *(pEventData0 + i));
+		printk(BIOS_DEBUG, " %02x ", *(pEventData0 + i));
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
 }
 
@@ -119,7 +119,7 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u16 link, u8 **List)
 	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 	/* If the BUID was adjusted in early_ht we need to do the manual override */
 	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
-		printk_debug("AMD_CB_ManualBUIDSwapList()\n");
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 		if ((node == 0) && (link == 0)) {	/* BSP SB link */
 			*List = swaplist;
 			return 1;
@@ -170,9 +170,9 @@ void amd_ht_init(struct sys_info *sysinfo)
 		AMD_CB_EventNotify	// void (*AMD_CB_EventNotify) ();
 	};
 
-	printk_debug("Enter amd_ht_init()\n");
+	printk(BIOS_DEBUG, "Enter amd_ht_init()\n");
 	amdHtInitialize(&ht_wrapper);
-	printk_debug("Exit amd_ht_init()\n");
+	printk(BIOS_DEBUG, "Exit amd_ht_init()\n");
 
 
 }
diff --git a/src/northbridge/amd/amdk8/amdk8_acpi.c b/src/northbridge/amd/amdk8/amdk8_acpi.c
index b5062bd092..1257f86633 100644
--- a/src/northbridge/amd/amdk8/amdk8_acpi.c
+++ b/src/northbridge/amd/amdk8/amdk8_acpi.c
@@ -81,7 +81,7 @@ unsigned long acpi_create_srat_lapics(unsigned long current)
 		if (!cpu->enabled) {
 			continue;
 		}
-		printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
+		printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.apic.node_id, cpu->path.apic.apic_id);
 		cpu_index++;
 	}
@@ -110,7 +110,7 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
 	basek = resk(res->base);
 	sizek = resk(res->size);
 
-	printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
+	printk(BIOS_DEBUG, "set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
 		     dev_path(dev), res->index, basek, sizek);
 	/*
 	 * 0-640K must be on node 0
diff --git a/src/northbridge/amd/amdk8/amdk8_f.h b/src/northbridge/amd/amdk8/amdk8_f.h
index 7010e80bd6..db2cf8a317 100644
--- a/src/northbridge/amd/amdk8/amdk8_f.h
+++ b/src/northbridge/amd/amdk8/amdk8_f.h
@@ -565,7 +565,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 #ifdef __PRE_RAM__
 		print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n");
 #else
-		printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 
+		printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]); 
 #endif
 		switch(sysinfo->mem_trained[i]) {
 		case 0: //don't need train
@@ -583,7 +583,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 		print_debug("mem trained failed\r\n");
 		soft_reset();
 #else
-		printk_debug("mem trained failed\n"); 
+		printk(BIOS_DEBUG, "mem trained failed\n"); 
 		hard_reset();
 #endif
 	}
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 45b5a044f8..66876c2148 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -111,7 +111,7 @@
 
 static inline void print_linkn (const char *strval, uint8_t byteval)
 {
-	printk_debug("%s%02x\r\n", strval, byteval);
+	printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval);
 }
 
 static void disable_probes(void)
@@ -1496,7 +1496,7 @@ static unsigned setup_smp(void)
 		nodes = setup_smp8();
 #endif
 
-	printk_debug("%02x nodes initialized.\r\n", nodes);
+	printk(BIOS_DEBUG, "%02x nodes initialized.\r\n", nodes);
 
 	return nodes;
 }
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index acfd602c6d..ff2f347af1 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -10,14 +10,14 @@
 static inline void print_debug_addr(const char *str, void *val)
 {
 #if CACHE_AS_RAM_ADDRESS_DEBUG == 1
-		printk_debug("------Address debug: %s%x------\n", str, val);
+		printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
 #endif
 }
 
 #if 1
 static void print_debug_pci_dev(unsigned dev)
 {
-	printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
+	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 }
 
 static void print_pci_devices(void)
@@ -34,7 +34,7 @@ static void print_pci_devices(void)
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
+		printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16));
 		if(((dev>>12) & 0x07) == 0) {
 			uint8_t hdr_type;
 			hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
@@ -53,10 +53,10 @@ static void dump_pci_device(unsigned dev)
 	for(i = 0; i < 256; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("\n%02x:",i);
+			printk(BIOS_DEBUG, "\n%02x:",i);
 		}
 		val = pci_read_config8(dev, i);
-		printk_debug(" %02x", val);
+		printk(BIOS_DEBUG, " %02x", val);
 	}
 	print_debug("\n");
 }
@@ -72,10 +72,10 @@ static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
 	for(i = 0; i < 0x40; i++) {
 		uint32_t val;
 		int j;
-		printk_debug("\n%02x:",i);
+		printk(BIOS_DEBUG, "\n%02x:",i);
 		val = pci_read_config32_index_wait(dev, index_reg, i);
 		for(j=0;j<4;j++) {
-			printk_debug(" %02x", val & 0xff);
+			printk(BIOS_DEBUG, " %02x", val & 0xff);
 			val >>= 8;
 		}
 
@@ -145,38 +145,38 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
 		device = ctrl->channel0[i];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.0: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
 			int j;
-			printk_debug("dimm: %02x.1: %02x", i, device);
+			printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
 			for(j = 0; j < 128; j++) {
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					printk_debug("\n%02x: ", j);
+					printk(BIOS_DEBUG, "\n%02x: ", j);
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
 					break;
 				}
 				byte = status & 0xff;
-				printk_debug("%02x ", byte);
+				printk(BIOS_DEBUG, "%02x ", byte);
 			}
 			print_debug("\n");
 		}
@@ -189,7 +189,7 @@ static void dump_smbus_registers(void)
 	for(device = 1; device < 0x80; device++) {
 		int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
-		printk_debug("smbus: %02x", device);
+		printk(BIOS_DEBUG, "smbus: %02x", device);
 		for(j = 0; j < 256; j++) {
 			int status;
 			unsigned char byte;
@@ -198,10 +198,10 @@ static void dump_smbus_registers(void)
 				break;
 			}
 			if ((j & 0xf) == 0) {
-				printk_debug("\n%02x: ",j);
+				printk(BIOS_DEBUG, "\n%02x: ",j);
 			}
 			byte = status & 0xff;
-			printk_debug("%02x ", byte);
+			printk(BIOS_DEBUG, "%02x ", byte);
 		}
 		print_debug("\n");
 	}
@@ -213,14 +213,14 @@ static void dump_io_resources(unsigned port)
 
 	int i;
 	udelay(2000);
-	printk_debug("%04x:\n", port);
+	printk(BIOS_DEBUG, "%04x:\n", port);
 	for(i=0;i<256;i++) {
 		uint8_t val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("%02x:", i);
+			printk(BIOS_DEBUG, "%02x:", i);
 		}
 		val = inb(port);
-		printk_debug(" %02x",val);
+		printk(BIOS_DEBUG, " %02x",val);
 		if ((i & 0x0f) == 0x0f) {
 			print_debug("\n");
 		}
@@ -234,9 +234,9 @@ static void dump_mem(unsigned start, unsigned end)
 	print_debug("dump_mem:");
 	for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
 	}
 	print_debug("\n");
  }
diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c
index 8b9a9d4fb4..cf8937aab7 100644
--- a/src/northbridge/amd/amdk8/exit_from_self.c
+++ b/src/northbridge/amd/amdk8/exit_from_self.c
@@ -43,7 +43,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			u32 mnc;
-			printk_spew("ECC enabled\n");
+			printk(BIOS_SPEW, "ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_Width128) {
@@ -52,7 +52,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 			pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
 		}
 
-		printk_debug("before resume errata #%d\n",
+		printk(BIOS_DEBUG, "before resume errata #%d\n",
 			     (is_post_rev_g) ? 270 : 125);
 		/* 
 		   1. Restore memory controller registers as normal.
@@ -70,7 +70,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 		enable_lapic();
 		init_timer();
 
-		printk_debug("before exit errata - timer enabled\n");
+		printk(BIOS_DEBUG, "before exit errata - timer enabled\n");
 
 		if (is_post_rev_g) {
 			dcl =
@@ -86,7 +86,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 
 		udelay(800);
 
-		printk_debug("before exit errata - after mdelay\n");
+		printk(BIOS_DEBUG, "before exit errata - after mdelay\n");
 
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_INIT);
 		dcl &= ~DI_EnDramInit;
@@ -108,7 +108,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 		pcidev =
 		    0x80000000 | ((((ctrl[i].node_id + 0x18) << 3) | 0x2)
 				  << 8) | 0x90;
-		printk_debug("pcidev is %x\n", pcidev);
+		printk(BIOS_DEBUG, "pcidev is %x\n", pcidev);
 		bitmask = 2;
 		__asm__ __volatile__("pushl %0\n\t"
 				     "movw $0xcf8, %%dx\n\t"
@@ -125,7 +125,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 				     "q"(bitmask):"edx");
 	}
 
-	printk_debug("after exit errata\n");
+	printk(BIOS_DEBUG, "after exit errata\n");
 
 
 	for (i = 0; i < controllers; i++) {
@@ -136,12 +136,12 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 		if (sysinfo->meminfo[i].dimm_mask == 0x00)
 			continue;
 
-		printk_debug("Exiting memory from self refresh: ");
+		printk(BIOS_DEBUG, "Exiting memory from self refresh: ");
 		int loops = 0;
 		do {
 			loops++;
 			if ((loops & 1023) == 0) {
-				printk_debug(".");
+				printk(BIOS_DEBUG, ".");
 			}
 			dcm =
 			    pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
@@ -149,11 +149,11 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 			  0) /* || ((dcm & DCM_DramEnabled) == 0) */ );
 
 		if (loops >= TIMEOUT_LOOPS) {
-			printk_debug("timeout with with cntrl[%d]\n", i);
+			printk(BIOS_DEBUG, "timeout with with cntrl[%d]\n", i);
 			continue;
 		}
 
-		printk_debug(" done\n");
+		printk(BIOS_DEBUG, " done\n");
 	}
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
index 737f33b48d..aa10f3f947 100644
--- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c
+++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
@@ -55,7 +55,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
 		dst_link = (config_map >> 8) & 3;
 		bus_base = (config_map >> 16) & 0xff;
 #if 0
-		printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+		printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
 			dst_node, dst_link, bus_base,
 			reg, config_map);
 #endif
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 4dc302b49d..2e68618100 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -26,7 +26,7 @@
 
 static inline void print_linkn_in (const char *strval, uint8_t byteval)
 {
-	printk_debug("%s%02x\r\n", strval, byteval);
+	printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval);
 }
 
 static uint8_t ht_lookup_capability(device_t dev, uint16_t val)
@@ -127,7 +127,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
 	uint32_t id;
 
 	freq_cap = pci_read_config16(dev, pos);
-	printk_spew("pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap);
+	printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap);
 	freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
 
 	id = pci_read_config32(dev, 0);
@@ -157,8 +157,8 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
 	#endif
 	}
 
-	printk_spew("pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap);
-	//printk_spew("capping to 800/600/400/200 MHz\r\n");
+	printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap);
+	//printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\r\n");
 	//freq_cap &= 0x3f;
 	return freq_cap;
 }
@@ -220,14 +220,14 @@ static int ht_optimize_link(
 	int needs_reset;
 	/* Set link width and frequency */
 
-	printk_spew("entering ht_optimize_link\r\n");
+	printk(BIOS_SPEW, "entering ht_optimize_link\r\n");
 	/* Initially assume everything is already optimized and I don't need a reset */
 	needs_reset = 0;
 
 	/* Get the frequency capabilities */
 	freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1));
 	freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2));
-	printk_spew("freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2);
+	printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2);
 
 	/* Calculate the highest possible frequency */
 	freq = log2(freq_cap1 & freq_cap2);
@@ -236,11 +236,11 @@ static int ht_optimize_link(
 	old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1));
 	old_freq &= 0x0f;
 	needs_reset |= old_freq != freq;
-	printk_spew("dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+	printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
 	old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2));
 	old_freq &= 0x0f;
 	needs_reset |= old_freq != freq;
-	printk_spew("dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+	printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
 
 	/* Set the Calculated link frequency */
 	pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq);
@@ -249,45 +249,45 @@ static int ht_optimize_link(
 	/* Get the width capabilities */
 	width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1));
 	width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2));
-	printk_spew("width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2);
+	printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2);
 
 	/* Calculate dev1's input width */
 	ln_width1 = link_width_to_pow2[width_cap1 & 7];
 	ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
-	printk_spew("dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+	printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
 	if (ln_width1 > ln_width2) {
 		ln_width1 = ln_width2;
 	}
 	width = pow2_to_link_width[ln_width1];
-	printk_spew("dev1 input width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "dev1 input width=0x%x\r\n", width);
 	/* Calculate dev1's output width */
 	ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
 	ln_width2 = link_width_to_pow2[width_cap2 & 7];
-	printk_spew("dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+	printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
 	if (ln_width1 > ln_width2) {
 		ln_width1 = ln_width2;
 	}
 	width |= pow2_to_link_width[ln_width1] << 4;
-	printk_spew("dev1 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "dev1 input|output width=0x%x\r\n", width);
 
 	/* See if I am changing dev1's width */
 	old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1);
 	old_width &= 0x77;
 	needs_reset |= old_width != width;
-	printk_spew("old dev1 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "old dev1 input|output width=0x%x\r\n", width);
 
 	/* Set dev1's widths */
 	pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
 
 	/* Calculate dev2's width */
 	width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
-	printk_spew("dev2 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "dev2 input|output width=0x%x\r\n", width);
 
 	/* See if I am changing dev2's width */
 	old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1);
 	old_width &= 0x77;
 	needs_reset |= old_width != width;
-	printk_spew("old dev2 input|output width=0x%x\r\n", width);
+	printk(BIOS_SPEW, "old dev2 input|output width=0x%x\r\n", width);
 
 	/* Set dev2's widths */
 	pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width);
@@ -852,16 +852,16 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
 
 	unsigned link_pair_num = sysinfo->link_pair_num;
 
-	printk_spew("entering optimize_link_incoherent_ht\r\n");
-	printk_spew("sysinfo->link_pair_num=0x%x\r\n", link_pair_num);
+	printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\r\n");
+	printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\r\n", link_pair_num);
 	for(i=0; i< link_pair_num; i++) {
 		struct link_pair_st *link_pair= &sysinfo->link_pair[i];
 		reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
-		printk_spew("after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed);
+		printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed);
 	}
 
 	reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num);
-	printk_spew("after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed);
+	printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed);
 
 	return reset_needed;
 
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index a1e88aa837..1b40eb1381 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -112,7 +112,7 @@ static void misc_control_init(struct device *dev)
 	int needs_reset;
 	struct device *f0_dev, *f2_dev;
 	
-	printk_debug("NB: Function 3 Misc Control.. ");
+	printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 	needs_reset = 0;
 
 	/* Disable Machine checks from Invalid Locations.
@@ -205,13 +205,13 @@ static void misc_control_init(struct device *dev)
 		}
 	}
 	else {
-		printk_err("Missing f0 device!\n");
+		printk(BIOS_ERR, "Missing f0 device!\n");
 	}
 	if (needs_reset) {
-		printk_debug("resetting cpu\n");
+		printk(BIOS_DEBUG, "resetting cpu\n");
 		hard_reset();
 	}
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 }
 
 
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 1dd71de10e..2ca14444cb 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -395,14 +395,14 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
 
 	/* Make certain the resource has actually been set */
 	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		printk_err("%s: can't set unassigned resource @%lx %lx\n",
+		printk(BIOS_ERR, "%s: can't set unassigned resource @%lx %lx\n",
 			   __func__, resource->index, resource->flags);
 		return;
 	}
 
 	/* If I have already stored this resource don't worry about it */
 	if (resource->flags & IORESOURCE_STORED) {
-		printk_err("%s: can't set stored resource @%lx %lx\n", __func__,
+		printk(BIOS_ERR, "%s: can't set stored resource @%lx %lx\n", __func__,
 			   resource->index, resource->flags);
 		return;
 	}
@@ -442,7 +442,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
 		limit |= (nodeid & 7);
 
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-			printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
+			printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
 				    __func__, dev_path(dev), link);
 			base |= PCI_IO_BASE_VGA_EN;
 		}
@@ -487,7 +487,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
 	for (link = 0; link < dev->links; link++) {
 		if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
 #if CONFIG_CONSOLE_VGA_MULTI == 1
-			printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
+			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
 				dev->link[link].secondary,dev->link[link].subordinate);
 			/* We need to make sure the vga_pri is under the link */
 			if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
@@ -502,12 +502,12 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
 	if (link == dev->links)
 		return;
 
-	printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
+	printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
 
 	/* allocate a temp resource for the legacy VGA buffer */
 	resource = new_resource(dev, IOINDEX(4, link));
 	if(!resource){
-		printk_debug("VGA: %s out of resources.\n", dev_path(dev));
+		printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev));
 		return;
 	}
 	resource->base = 0xa0000;
@@ -573,10 +573,10 @@ static void amdk8_enable_resources(device_t dev)
 static void mcf0_control_init(struct device *dev)
 {
 #if 0
-	printk_debug("NB: Function 0 Misc Control.. ");
+	printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. ");
 #endif
 #if 0
-	printk_debug("done.\n");
+	printk(BIOS_DEBUG, "done.\n");
 #endif
 }
 
@@ -773,7 +773,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 	f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
 	dev = __f1_dev[node_id];
 	if (dev == NULL) {
-		printk_err("%s: node %x is NULL!\n", __func__, node_id);
+		printk(BIOS_ERR, "%s: node %x is NULL!\n", __func__, node_id);
 		return;
 	}
 	hoist = pci_read_config32(dev, 0xf0);
@@ -869,9 +869,9 @@ static void amdk8_domain_set_resources(device_t dev)
 	mem2 = find_resource(dev, 2);
 
 #if 1
-	printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem1->base, mem1->limit, mem1->size, mem1->align);
-	printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem2->base, mem2->limit, mem2->size, mem2->align);
 #endif
 
@@ -899,9 +899,9 @@ static void amdk8_domain_set_resources(device_t dev)
 	}
 
 #if 1
-	printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem1->base, mem1->limit, mem1->size, mem1->align);
-	printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+	printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
 		mem2->base, mem2->limit, mem2->size, mem2->align);
 #endif
 
@@ -1005,11 +1005,11 @@ static void amdk8_domain_set_resources(device_t dev)
 
 
 #if CONFIG_GFXUMA == 1
-		printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
+		printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
 		if ((uma_memory_base >> 10) < mmio_basek)
-			printk_alert("node %d: UMA memory starts below mmio_basek\n", i);
+			printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
 #else
-//		printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
+//		printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
 #endif
 
 		/* See if I need to split the region to accomodate pci memory space */
@@ -1030,7 +1030,7 @@ static void amdk8_domain_set_resources(device_t dev)
 						high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
 #endif
 						high_tables_size = HIGH_TABLES_SIZE * 1024;
-						printk_debug(" split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
+						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
 							     high_tables_base);
 					}
 #endif
@@ -1060,7 +1060,7 @@ static void amdk8_domain_set_resources(device_t dev)
 			ram_resource(dev, (idx | i), basek, sizek);
 		idx += 0x10;
 #if CONFIG_WRITE_HIGH_TABLES==1
-		printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
+		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
 			     i, mmio_basek, basek, limitk);
 		if (i==0 && high_tables_base==0) {
 		/* Leave some space for ACPI, PIRQ and MP tables */
@@ -1101,7 +1101,7 @@ static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max)
 			if (!dev->link[0].disable_relaxed_ordering) {
 				httc |= HTTC_RSP_PASS_PW;
 			}
-			printk_spew("%s passpw: %s\n",
+			printk(BIOS_SPEW, "%s passpw: %s\n",
 				dev_path(dev),
 				(!dev->link[0].disable_relaxed_ordering)?
 				"enabled":"disabled");
@@ -1207,7 +1207,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
 		if (cpu_dev && cpu_dev->enabled) {
 			j = pci_read_config32(cpu_dev, 0xe8);
 			j = (j >> 12) & 3; // dev is func 3
-			printk_debug("  %s siblings=%d\n", dev_path(cpu_dev), j);
+			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(cpu_dev), j);
 
 			if(nb_cfg_54) {
 				// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
@@ -1224,7 +1224,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
 				       e0_later_single_core = 0;
 	       			}
 				if(e0_later_single_core) {
-					printk_debug("\tFound Rev E or Rev F later single core\r\n");
+					printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n");
 
 					j=1;
 				}
@@ -1287,7 +1287,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
 						       cpu->path.apic.apic_id += sysconf.apicid_offset;
 					}
 				}
-				printk_debug("CPU: %s %s\n",
+				printk(BIOS_DEBUG, "CPU: %s %s\n",
 					dev_path(cpu), cpu->enabled?"enabled":"disabled");
 			}
 
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 0e27a16991..b02e9a0058 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -25,7 +25,7 @@ static void hard_reset(void);
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
-//	printk_debug("setting up resource map....");
+//	printk(BIOS_DEBUG, "setting up resource map....");
 	for (i = 0; i < max; i += 3) {
 		device_t dev;
 		unsigned where;
@@ -37,7 +37,7 @@ static void setup_resource_map(const unsigned int *register_values, int max)
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-//	printk_debug("done.\n");
+//	printk(BIOS_DEBUG, "done.\n");
 }
 
 static int controller_present(const struct mem_controller *ctrl)
@@ -524,10 +524,10 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	int max;
 
 	if (!controller_present(ctrl)) {
-//		printk_debug("No memory controller present\n");
+//		printk(BIOS_DEBUG, "No memory controller present\n");
 		return;
 	}
-	printk_spew("setting up CPU%02x northbridge registers\n", ctrl->node_id);
+	printk(BIOS_SPEW, "setting up CPU%02x northbridge registers\n", ctrl->node_id);
 	max = ARRAY_SIZE(register_values);
 	for (i = 0; i < max; i += 3) {
 		device_t dev;
@@ -540,7 +540,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	printk_spew("done.\n");
+	printk(BIOS_SPEW, "done.\n");
 }
 
 static void hw_enable_ecc(const struct mem_controller *ctrl)
@@ -849,17 +849,17 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
 	}
 
 	/* Report the amount of memory. */
-	printk_debug("RAM end at 0x%08x kB\n", tom_k);
+	printk(BIOS_DEBUG, "RAM end at 0x%08x kB\n", tom_k);
 
 	/* Now set top of memory */
 	msr_t msr;
 	if (tom_k > (4*1024*1024)) {
-		printk_spew("Handling memory mapped above 4 GB\n");
-		printk_spew("Upper RAM end at 0x%08x kB\n", tom_k);
+		printk(BIOS_SPEW, "Handling memory mapped above 4 GB\n");
+		printk(BIOS_SPEW, "Upper RAM end at 0x%08x kB\n", tom_k);
 		msr.lo = (tom_k & 0x003fffff) << 10;
 		msr.hi = (tom_k & 0xffc00000) >> 22;
 		wrmsr(TOP_MEM2, msr);
-		printk_spew("Correcting memory amount mapped below 4 GB\n");
+		printk(BIOS_SPEW, "Correcting memory amount mapped below 4 GB\n");
 	}
 
 	/* Leave a 64M hole between TOP_MEM and TOP_MEM2
@@ -872,9 +872,9 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
 		} else
 #endif
 		tom_k = 0x3f0000;
-		printk_spew("Adjusting lower RAM end\n");
+		printk(BIOS_SPEW, "Adjusting lower RAM end\n");
 	}
-	printk_spew("Lower RAM end at 0x%08x kB\n", tom_k);
+	printk(BIOS_SPEW, "Lower RAM end at 0x%08x kB\n", tom_k);
 	msr.lo = (tom_k & 0x003fffff) << 10;
 	msr.hi = (tom_k & 0xffc00000) >> 22;
 	wrmsr(TOP_MEM, msr);
@@ -969,7 +969,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
 		if (is_dual_channel(ctrl)) {
 		/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
 			if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
-//     				printk_debug("8 4GB chip selects cannot be interleaved\n");
+//     				printk(BIOS_DEBUG, "8 4GB chip selects cannot be interleaved\n");
 				return 0;
 			}
 			csbase_inc <<=1;
@@ -979,7 +979,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
 		csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
 		if (is_dual_channel(ctrl)) {
 			if ( (bits==3) && (common_cs_mode > 8)) {
-//				printk_debug("8 cs_mode>8 chip selects cannot be interleaved\n");
+//				printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\n");
 				return 0;
 			}
 			csbase_inc <<=1;
@@ -1006,7 +1006,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
 		csbase += csbase_inc;
 	}
 
-	printk_spew("Interleaved\n");
+	printk(BIOS_SPEW, "Interleaved\n");
 
 	/* Return the memory size in K */
 	return common_size << (15 + bits);
@@ -1107,7 +1107,7 @@ static void order_dimms(const struct mem_controller *ctrl)
 	    read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
 		tom_k = interleave_chip_selects(ctrl);
 	} else {
-		printk_debug("Interleaving disabled\n");
+		printk(BIOS_DEBUG, "Interleaving disabled\n");
 		tom_k = 0;
 	}
 
@@ -1124,7 +1124,7 @@ static void order_dimms(const struct mem_controller *ctrl)
 
 static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
 {
-	printk_debug("disabling dimm %02x\n", index);
+	printk(BIOS_DEBUG, "disabling dimm %02x\n", index);
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
 	dimm_mask &= ~(1 << index);
@@ -1183,9 +1183,9 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 
 	if (is_registered(ctrl)) {
-		printk_spew("Registered\n");
+		printk(BIOS_SPEW, "Registered\n");
 	} else {
-		printk_spew("Unbuffered\n");
+		printk(BIOS_SPEW, "Unbuffered\n");
 	}
 
 	return dimm_mask;
@@ -1280,7 +1280,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma
 			}
 		}
 	}
-	printk_spew("Enabling dual channel memory\n");
+	printk(BIOS_SPEW, "Enabling dual channel memory\n");
 	uint32_t dcl;
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_32ByteEn;
@@ -1378,7 +1378,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
 	if (!param->cycle_time) {
 		die("min_cycle_time to low");
 	}
-	printk_spew("%s\n", param->name);
+	printk(BIOS_SPEW, "%s\n", param->name);
 	return param;
 }
 
@@ -2073,7 +2073,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 	long dimm_mask;
 #if 1
 	if (!controller_present(ctrl)) {
-//		printk_debug("No memory controller present\n");
+//		printk(BIOS_DEBUG, "No memory controller present\n");
 		return;
 	}
 #endif
@@ -2081,7 +2081,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 	activate_spd_rom(ctrl);
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		printk_debug("No memory for this cpu\n");
+		printk(BIOS_DEBUG, "No memory for this cpu\n");
 		return;
 	}
 	dimm_mask = spd_enable_2channels(ctrl, dimm_mask);
@@ -2105,7 +2105,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 	return;
  hw_spd_err:
 	/* Unrecoverable error reading SPD data */
-	printk_err("SPD error - reset\n");
+	printk(BIOS_ERR, "SPD error - reset\n");
 	hard_reset();
 	return;
 }
@@ -2171,7 +2171,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
 
 	hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
 
-	printk_spew("Handling memory hole at 0x%08x (default)\n", hole_startk);
+	printk(BIOS_SPEW, "Handling memory hole at 0x%08x (default)\n", hole_startk);
 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
 	/* We need to double check if hole_startk is valid.
 	 * If it is equal to the dram base address in K (base_k),
@@ -2196,7 +2196,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
 			basek_pri = base_k;
 	}
 
-	printk_spew("Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
+	printk(BIOS_SPEW, "Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
 #endif
 	/* Find node number that needs the memory hole configured */
 	for (i=0; i<controllers; i++) {
@@ -2273,7 +2273,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			uint32_t mnc;
-			printk_spew("ECC enabled\n");
+			printk(BIOS_SPEW, "ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_128BitEn) {
@@ -2301,17 +2301,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 			continue;
 		}
 
-		printk_debug("Initializing memory: ");
+		printk(BIOS_DEBUG, "Initializing memory: ");
 		int loops = 0;
 		do {
 			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 			loops++;
 			if ((loops & 1023) == 0) {
-				printk_debug(".");
+				printk(BIOS_DEBUG, ".");
 			}
 		} while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
 		if (loops >= TIMEOUT_LOOPS) {
-			printk_debug(" failed\n");
+			printk(BIOS_DEBUG, " failed\n");
 			continue;
 		}
 
@@ -2324,7 +2324,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 			} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
 		}
 
-		printk_debug(" done\n");
+		printk(BIOS_DEBUG, " done\n");
 	}
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 601c035dd8..c38d1595ae 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -34,7 +34,7 @@
 #endif
 
 #if DEBUG_RAM_SETUP
-#define printk_raminit printk_debug
+#define printk_raminit(fmt, arg...) printk(BIOS_DEBUG, fmt, arg)
 #else
 #define printk_raminit(fmt, arg...)
 #endif
@@ -691,7 +691,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 	}
 	sysinfo->ctrl_present[ctrl->node_id] = 1;
 
-	printk_spew("setting up CPU %02x northbridge registers\n", ctrl->node_id);
+	printk(BIOS_SPEW, "setting up CPU %02x northbridge registers\n", ctrl->node_id);
 	max = ARRAY_SIZE(register_values);
 	for (i = 0; i < max; i += 3) {
 		device_t dev;
@@ -704,7 +704,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	printk_spew("done.\n");
+	printk(BIOS_SPEW, "done.\n");
 }
 
 static int is_dual_channel(const struct mem_controller *ctrl)
@@ -801,7 +801,7 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
 	if (value <=4 ) value += 8; // add back to 1G to high
 	value += (27-5); // make 128MB to the real lines
 	if ( value != (sz->per_rank)) {
-		printk_err("Bad RANK Size --\n");
+		printk(BIOS_ERR, "Bad RANK Size --\n");
 		goto val_err;
 	}
 
@@ -1041,7 +1041,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk)
 	}
 
 	/* Report the amount of memory. */
-	printk_debug("RAM end at 0x%08x kB\n", tom_k);
+	printk(BIOS_DEBUG, "RAM end at 0x%08x kB\n", tom_k);
 
 	/* Now set top of memory */
 	msr_t msr;
@@ -1175,7 +1175,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
 		csbase += csbase_inc;
 	}
 
-	printk_debug("Interleaved\n");
+	printk(BIOS_DEBUG, "Interleaved\n");
 
 	/* Return the memory size in K */
 	return common_size << ((27-10) + bits);
@@ -1279,7 +1279,7 @@ static void order_dimms(const struct mem_controller *ctrl,
 	    CMOS_VLEN_interleave_chip_selects, 1) != 0) {
 		tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
 	} else {
-		printk_debug("Interleaving disabled\n");
+		printk(BIOS_DEBUG, "Interleaving disabled\n");
 		tom_k = 0;
 	}
 
@@ -1297,7 +1297,7 @@ static void order_dimms(const struct mem_controller *ctrl,
 static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
 			  struct mem_info *meminfo)
 {
-	printk_debug("disabling dimm %02x\n", index);
+	printk(BIOS_DEBUG, "disabling dimm %02x\n", index);
 	if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);
 		pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);
@@ -1370,9 +1370,9 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 
 	if (meminfo->is_registered) {
-		printk_spew("Registered\n");
+		printk(BIOS_SPEW, "Registered\n");
 	} else {
-		printk_spew("Unbuffered\n");
+		printk(BIOS_SPEW, "Unbuffered\n");
 	}
 	return meminfo->dimm_mask;
 }
@@ -1473,7 +1473,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
 		/* Abort if the chips don't support a common CAS latency. */
 		common_cl = spd_read_byte(device0, 18) & spd_read_byte(device1, 18);
 		if (!common_cl) {
-			printk_debug("No common CAS latency supported\n");
+			printk(BIOS_DEBUG, "No common CAS latency supported\n");
 			goto single_channel;
 		} else {
 			printk_raminit("Common CAS latency bitfield: 0x%02x\n", common_cl);
@@ -1495,7 +1495,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
 			}
 		}
 	}
-	printk_spew("Enabling dual channel memory\n");
+	printk(BIOS_SPEW, "Enabling dual channel memory\n");
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_BurstLength32;  /*	32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses
 					32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode	*/
@@ -1514,7 +1514,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
 		if (((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
 			/* mux capable and single dimm in channelB */
 			if (mux_cap) {
-				printk_spew("Enable 64MuxMode & BurstLength32\n");
+				printk(BIOS_SPEW, "Enable 64MuxMode & BurstLength32\n");
 				dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
 				dcm |= DCM_Mode64BitMux;
 				pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
@@ -1529,7 +1529,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
 	} else { /* unmatched dual dimms ? */
 		/* unmatched dual dimms not supported by meminit code. Use single channelA dimm. */
 		meminfo->dimm_mask &= ~((1 << (DIMM_SOCKETS * 2)) - (1 << DIMM_SOCKETS));
-		printk_spew("Unmatched dual dimms. Use single channelA dimm.\n");
+		printk(BIOS_SPEW, "Unmatched dual dimms. Use single channelA dimm.\n");
 	}
 	return meminfo->dimm_mask;
 }
@@ -1610,7 +1610,7 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time)
 	if (!param->cycle_time) {
 		die("min_cycle_time to low");
 	}
-	printk_spew("%s\n", param->name);
+	printk(BIOS_SPEW, "%s\n", param->name);
 	return param;
 }
 
@@ -1912,7 +1912,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 	value |= result.param->dch_memclk << DCH_MemClkFreq_SHIFT;
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
 
-	printk_debug("%s\n", result.param->name);
+	printk(BIOS_DEBUG, "%s\n", result.param->name);
 
 	/* Update DRAM Timing Low with our selected cas latency */
 	value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
@@ -1960,7 +1960,7 @@ int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param)
 
 	if (clocks < DTL_TRC_MIN) {
 #warning We should die here or at least disable this bank.
-		printk_notice("update_dimm_Trc: can't refresh fast enough, "
+		printk(BIOS_NOTICE, "update_dimm_Trc: can't refresh fast enough, "
 			"want %i clocks, can %i clocks\n", clocks, DTL_TRC_MIN);
 		clocks = DTL_TRC_MIN;
 	}
@@ -2057,7 +2057,7 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me
 	}
 	
 	if (clocks > TT_MAX) {
-		printk_info("warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
+		printk(BIOS_INFO, "warning spd byte : %x = %x > TT_MAX: %x, setting TT_MAX", SPD_TT, value, TT_MAX);
 		clocks = TT_MAX;
 	}
 
@@ -2372,7 +2372,7 @@ static void set_ecc(const struct mem_controller *ctrl,
 		if (!(meminfo->dimm_mask & (1 << i))) {
 			if (meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) { /* channelB only? */
 				spd_device = ctrl->channel1[i];
-				printk_debug("set_ecc spd_device: 0x%x\n", spd_device);
+				printk(BIOS_DEBUG, "set_ecc spd_device: 0x%x\n", spd_device);
 			} else {
 				continue;
 			}
@@ -2405,7 +2405,7 @@ static void set_TT(const struct mem_controller *ctrl,
 	uint32_t reg;
 
 	if ((val < TT_MIN) || (val > TT_MAX)) {
-		printk_err(str);
+		printk(BIOS_ERR, str);
 		die(" Unknown\n");
 	}
 
@@ -2765,7 +2765,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl,
 
 		continue;
 	dimm_err:
-		printk_debug("spd_set_dram_timing dimm_err!\n");
+		printk(BIOS_DEBUG, "spd_set_dram_timing dimm_err!\n");
 		if (rc < 0) {
 			return -1;
 		}
@@ -2815,7 +2815,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl,
 #endif
 	meminfo = &sysinfo->meminfo[ctrl->node_id];
 
-	printk_debug("sdram_set_spd_registers: paramx :%p\n", &paramx);
+	printk(BIOS_DEBUG, "sdram_set_spd_registers: paramx :%p\n", &paramx);
 
 	activate_spd_rom(ctrl);
 	meminfo->dimm_mask = spd_detect_dimms(ctrl);
@@ -2824,7 +2824,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl,
 
 	if (!(meminfo->dimm_mask & ((1 << 2*DIMM_SOCKETS) - 1)))
 	{
-		printk_debug("No memory for this cpu\n");
+		printk(BIOS_DEBUG, "No memory for this cpu\n");
 		return;
 	}
 	meminfo->dimm_mask = spd_enable_2channels(ctrl, meminfo);
@@ -3000,7 +3000,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 	/* FIXME: How about 32 node machine later? */
 	tsc_t tsc, tsc0[8];
 
-	printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]);
+	printk(BIOS_DEBUG, "sdram_enable: tsc0[8]: %p", &tsc0[0]);
 	uint32_t dword;
 #endif
 
@@ -3034,9 +3034,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 
 	/* lets override the rest of the routine */
 	if (suspend) {
-		printk_debug("Wakeup!\n");
+		printk(BIOS_DEBUG, "Wakeup!\n");
 		exit_from_self(controllers, ctrl, sysinfo);
-		printk_debug("Mem running !\n");
+		printk(BIOS_DEBUG, "Mem running !\n");
 		return;
 	}
 
@@ -3054,7 +3054,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			uint32_t mnc;
-			printk_spew("ECC enabled\n");
+			printk(BIOS_SPEW, "ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_Width128) {
@@ -3089,17 +3089,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 		/* Skip everything if I don't have any memory on this controller */
 		if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("Initializing memory: ");
+		printk(BIOS_DEBUG, "Initializing memory: ");
 		int loops = 0;
 		do {
 			dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 			loops++;
 			if ((loops & 1023) == 0) {
-				printk_debug(".");
+				printk(BIOS_DEBUG, ".");
 			}
 		} while(((dcl & DCL_InitDram) != 0) && (loops < TIMEOUT_LOOPS));
 		if (loops >= TIMEOUT_LOOPS) {
-			printk_debug(" failed\n");
+			printk(BIOS_DEBUG, " failed\n");
 			continue;
 		}
 
@@ -3127,7 +3127,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 			print_debug_dqs_tsc("     dtsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
 		}
 #endif
-		printk_debug(" done\n");
+		printk(BIOS_DEBUG, " done\n");
 	}
 
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 6ff7a95044..89ccf907cb 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -25,7 +25,7 @@ static inline void print_debug_dqs(const char *str, unsigned val, unsigned level
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s%x\r\n", str, val);
+		printk(BIOS_DEBUG, "%s%x\r\n", str, val);
 	}
 #endif
 }
@@ -34,7 +34,7 @@ static inline void print_debug_dqs_pair(const char *str, unsigned val, const cha
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2);
+		printk(BIOS_DEBUG, "%s%08x%s%08x\r\n", str, val, str2, val2);
 	}
 #endif
 }
@@ -43,14 +43,14 @@ static inline void print_debug_dqs_tsc(const char *str, unsigned i, unsigned val
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+		printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
 	}
 #endif
 }
 
 static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2)
 {
-	printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+	printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
 
 }
 
@@ -854,7 +854,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
 
 #if CONFIG_MEM_TRAIN_SEQ != 1
 	/* We need tidy output for type 1 */
-	printk_debug(" CTLRMaxDelay=%02x\n", CTLRMaxDelay);
+	printk(BIOS_DEBUG, " CTLRMaxDelay=%02x\n", CTLRMaxDelay);
 #endif
 
 	return (CTLRMaxDelay==0xae)?1:0;
@@ -1130,7 +1130,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
 
 	print_debug_dqs("\t\t\tTrainDQSPos begin ", 0, 3);
 
-	printk_debug("TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW);
+	printk(BIOS_DEBUG, "TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW);
 
 	for(DQSDelay=0; DQSDelay<48; DQSDelay++) {
 		MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS)
@@ -1403,7 +1403,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in
 
 	print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
 
-	printk_debug("TrainDQSRdWrPos: buf_a:%p\n", buf_a);
+	printk(BIOS_DEBUG, "TrainDQSRdWrPos: buf_a:%p\n", buf_a);
 
 	Errors = 0;
 	channel = 0;
@@ -1537,7 +1537,7 @@ static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info
 {
 	print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
 	if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) {
-		printk_err("\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id);
+		printk(BIOS_ERR, "\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id);
 		return 1;
 	}
 	else {
@@ -1700,7 +1700,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		}
 		sizek = 1 << align;
 #if CONFIG_MEM_TRAIN_SEQ != 1
-		printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n",
+		printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n",
 			reg, range_startk >>10, sizek >> 10,
 			(type==MTRR_TYPE_UNCACHEABLE)?"UC":
 			    ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
@@ -1895,7 +1895,7 @@ static void dqs_save_MC_NVRAM(unsigned int dev)
 {
 	int pos = 0;
 	u32 reg;
-	printk_debug("DQS SAVE NVRAM: %x\n", dev);
+	printk(BIOS_DEBUG, "DQS SAVE NVRAM: %x\n", dev);
 	pos = dqs_save_MC_NVRAM_ch(dev, 0, pos);
 	pos = dqs_save_MC_NVRAM_ch(dev, 1, pos);
 	/* save the maxasync lat here */
@@ -1908,7 +1908,7 @@ static void dqs_restore_MC_NVRAM(unsigned int dev)
 	int pos = 0;
 	u32 reg;
 
-	printk_debug("DQS RESTORE FROM NVRAM: %x\n", dev);
+	printk(BIOS_DEBUG, "DQS RESTORE FROM NVRAM: %x\n", dev);
 	pos = dqs_load_MC_NVRAM_ch(dev, 0, pos);
 	pos = dqs_load_MC_NVRAM_ch(dev, 1, pos);
 	/* load the maxasync lat here */
@@ -1950,9 +1950,9 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
 		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("DQS Training:RcvrEn:Pass1: %02x\n", i);
+		printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i);
 		if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
-       		printk_debug(" done\r\n");
+       		printk(BIOS_DEBUG, " done\r\n");
 	}
 
 	tsc[1] = rdtsc();
@@ -1968,9 +1968,9 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
 		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("DQS Training:DQSPos: %02x\n", i);
+		printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i);
 		if(train_DqsPos(ctrl+i, sysinfo)) goto out;
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 	}
 
 	tsc[3] = rdtsc();
@@ -1981,9 +1981,9 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
 		/* Skip everything if I don't have any memory on this controller */
 		if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
 
-		printk_debug("DQS Training:RcvrEn:Pass2: %02x\n", i);
+		printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i);
 		if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 		sysinfo->mem_trained[i]=1;
 		dqs_save_MC_NVRAM((ctrl+i)->f2);
 	}
@@ -2025,7 +2025,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
 	if(v) {
 		tsc[0] = rdtsc();
 
-		printk_debug("set DQS timing:RcvrEn:Pass1: %02x\n", i);
+		printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass1: %02x\n", i);
 	}
 	if(train_DqsRcvrEn(ctrl, 1,  sysinfo)) {
 		sysinfo->mem_trained[i]=0x81; //
@@ -2033,9 +2033,9 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 		tsc[1] = rdtsc();
-		printk_debug("set DQS timing:DQSPos: %02x\n", i);
+		printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i);
 	}
 
 	if(train_DqsPos(ctrl, sysinfo)) {
@@ -2044,10 +2044,10 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 		tsc[2] = rdtsc();
 
-		printk_debug("set DQS timing:RcvrEn:Pass2: %02x\n", i);
+		printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i);
 	}
 	if(train_DqsRcvrEn(ctrl, 2,  sysinfo)){
 		sysinfo->mem_trained[i]=0x83; //
@@ -2055,7 +2055,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk(BIOS_DEBUG, " done\r\n");
 
 		tsc[3] = rdtsc();
 	}
@@ -2106,7 +2106,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy
 	#endif
 		set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
 	#if CONFIG_AP_CODE_IN_CAR == 0
-		printk_debug("CODE IN ROM AND RUN ON NODE: %02x\n", nodeid);
+		printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid);
 		train_ram(nodeid, sysinfo, sysinfox);
 	#else
 		/* Can copy dqs_timing to ap cache and run from cache?
diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c
index 728ba88427..cd7b3b54b4 100644
--- a/src/northbridge/amd/amdk8/setup_resource_map.c
+++ b/src/northbridge/amd/amdk8/setup_resource_map.c
@@ -49,7 +49,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n",
 			i>>2, register_values[i],
 			register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
 			register_values[i+2],
@@ -129,7 +129,7 @@ static void setup_resource_map_x(const unsigned int *register_values, int max)
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
+		printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\r\n",
 			i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
 #endif
 		switch (register_values[i]) {
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 22e990255d..ec767fa27c 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -556,7 +556,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
 			base  += NextBase;
 			limit += NextBase;
 			DramSelBaseAddr += NextBase;
-			printk_debug(" Node: %02x  base: %02x  limit: %02x  BottomIO: %02x\n", Node, base, limit, BottomIO);
+			printk(BIOS_DEBUG, " Node: %02x  base: %02x  limit: %02x  BottomIO: %02x\n", Node, base, limit, BottomIO);
 
 			if (_MemHoleRemap) {
 				if ((base < BottomIO) && (limit >= BottomIO)) {
@@ -633,7 +633,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
 		devx = pDCTstat->dev_map;
 
 		if (pDCTstat->NodePresent) {
-		printk_debug(" Copy dram map from Node 0 to Node %02x \n", Node);
+		printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node);
 			reg = 0x40;		/*Dram Base 0*/
 			do {
 				val = Get_NB32(dev, reg);
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 7f8b8960fd..9dfccd9c4e 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -69,7 +69,7 @@ static void print_debug_dqs(const char *str, u32 val, u8 level)
 {
 #if DQS_TRAIN_DEBUG > 0
 	if (DQS_TRAIN_DEBUG >= level) {
-		printk_debug("%s%x\n", str, val);
+		printk(BIOS_DEBUG, "%s%x\n", str, val);
 	}
 #endif
 }
@@ -78,7 +78,7 @@ static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32
 {
 #if DQS_TRAIN_DEBUG > 0
 	if (DQS_TRAIN_DEBUG >= level) {
-		printk_debug("%s%08x%s%08x\n", str, val, str2, val2);
+		printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2);
 	}
 #endif
 }
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index 4eb02c7ded..1b0214d9fd 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -42,11 +42,11 @@ static void enable_shadow(device_t dev)
 
 static void northbridge_init(device_t dev) 
 {
-	printk_debug("northbridge: %s()\n", __func__);
+	printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
 	
 	optimize_xbus(dev);
 	enable_shadow(dev);
-	printk_spew("Calling enable_cache()\n");
+	printk(BIOS_SPEW, "Calling enable_cache()\n");
 	enable_cache();
 }
 
@@ -140,10 +140,10 @@ static void pci_domain_set_resources(device_t dev)
 		*bcdramtop = ((tomk << 10) - 1);
 		*mcgbaseadd = (tomk >> 9);
 
-		printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
-		printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
+		printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
+		printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
 
-		printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
+		printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
 
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
@@ -176,7 +176,7 @@ static struct device_operations pci_domain_ops = {
 
 static void cpu_bus_init(device_t dev)
 {
-	printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
+	printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
 	initialize_cpus(&dev->link[0]);
 }
 
@@ -194,18 +194,18 @@ static struct device_operations cpu_bus_ops = {
 
 static void enable_dev(struct device *dev)
 {
-        printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
+        printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
         /* Set the operations if it is a special bus type */
         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
-        	printk_spew("DEVICE_PATH_PCI_DOMAIN\n");
+        	printk(BIOS_SPEW, "DEVICE_PATH_PCI_DOMAIN\n");
                 dev->ops = &pci_domain_ops;
 		pci_set_method(dev);
         }
         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
-        	printk_spew("DEVICE_PATH_APIC_CLUSTER\n");
+        	printk(BIOS_SPEW, "DEVICE_PATH_APIC_CLUSTER\n");
                 dev->ops = &cpu_bus_ops;
         } else {
-        	printk_spew("device path type %d\n",dev->path.type);
+        	printk(BIOS_SPEW, "device path type %d\n",dev->path.type);
 	}
 }
 
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c
index 53a90535a5..cbb4e65620 100644
--- a/src/northbridge/amd/gx2/chipsetinit.c
+++ b/src/northbridge/amd/gx2/chipsetinit.c
@@ -87,7 +87,7 @@ static int is_5536(void){
 	msr_t msr;
 	msr = rdmsr(GLIU_SB_GLD_MSR_CAP);
 	msr.lo >>= 20;
-	printk_debug("is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf);
+	printk(BIOS_DEBUG, "is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf);
 	return ((msr.lo&0xf) == 5);
 }
 /* ***************************************************************************/
@@ -205,10 +205,10 @@ static void ChipsetFlashSetup(void)
 	int i;
 	int numEnabled = 0;
 
-	printk_debug("ChipsetFlashSetup++\n");
+	printk(BIOS_DEBUG, "ChipsetFlashSetup++\n");
 	for (i = 0; i < FlashInitTableLen; i++) {
 		if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
-			printk_debug("Enable CS%d\n", i);
+			printk(BIOS_DEBUG, "Enable CS%d\n", i);
 			/* we need to configure the memory/IO mask */
 			msr = rdmsr(FlashPort[i]);
 			msr.hi = 0;	/* start with the "enabled" bit clear */
@@ -221,13 +221,13 @@ static void ChipsetFlashSetup(void)
 			else
 				msr.hi &= ~0x00000004;
 			msr.hi |= FlashInitTable[i].fMask;
-			printk_debug("WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
+			printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
 			wrmsr(FlashPort[i], msr);
 
 			/* now write-enable the device */
 			msr = rdmsr(MDD_NORF_CNTRL);
 			msr.lo |= (1 << i);
-			printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
+			printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
 			wrmsr(MDD_NORF_CNTRL, msr);
 
 			/* update the number enabled */
@@ -239,10 +239,10 @@ static void ChipsetFlashSetup(void)
 	if (0 != numEnabled) {
 		msr = rdmsr(MDD_PIN_OPT);
 		msr.lo &= ~1; /* PIN_OPT_IDE */
-		printk_debug("WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
 		wrmsr(MDD_PIN_OPT, msr);
 	}
-	printk_debug("ChipsetFlashSetup--\n");
+	printk(BIOS_DEBUG, "ChipsetFlashSetup--\n");
 
 }
 
@@ -359,7 +359,7 @@ chipsetinit (struct northbridge_amd_gx2_config *nb){
 
 
 	/*  Flash Setup*/
-	printk_err("%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT");
+	printk(BIOS_ERR, "%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT");
 	if (nb->setupflash)
 		ChipsetFlashSetup();
 
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index b20d3d7829..274277d7fc 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -32,7 +32,7 @@ sizeram(void)
 	unsigned short dimm;
 
 	msr = rdmsr(0x20000018);
-	printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo);
 
 	/* dimm 0 */
 	dimm = msr.hi;
@@ -47,7 +47,7 @@ sizeram(void)
 	if ((dimm & 7) != 7)
 		sizem += (1 << ((dimm >> 12)-1)) * 8;
 
-	printk_debug("sizeram: sizem 0x%x\n", sizem);
+	printk(BIOS_DEBUG, "sizeram: sizem 0x%x\n", sizem);
 	return sizem;
 }
 
@@ -127,7 +127,7 @@ static void irq_init_steering(struct device *dev, uint16_t irq_map) {
 	/* Set up IRQ steering */
 	uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
 
-	printk_debug("%s(%08X [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
+	printk(BIOS_DEBUG, "%s(%08X [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
 
 	/* The IRQ steering values (in hex) are effectively dcba, where:
 	 *    <a> represents the IRQ for INTA, 
@@ -160,7 +160,7 @@ setup_gx2_cache(void)
 	int sizekbytes, sizereg;
 
 	sizekbytes = sizeram() * 1024;
-	printk_debug("setup_gx2_cache: enable for %d KB\n", sizekbytes);
+	printk(BIOS_DEBUG, "setup_gx2_cache: enable for %d KB\n", sizekbytes);
 	/* build up the rconf word. */
 	/* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
 	/* set romrp */
@@ -181,7 +181,7 @@ setup_gx2_cache(void)
 	val |= RAM_PROPERTIES;
 	msr.lo = val;
 	msr.hi = (val >> 32);
-	printk_debug("msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
 	wrmsr(CPU_RCONF_DEFAULT, msr);
 
 	enable_cache();
@@ -214,7 +214,7 @@ setup_gx2(void)
 
 #if 0
 	/* This has already been done elsewhere */
-	printk_debug("size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
+	printk(BIOS_DEBUG, "size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
 	msr.hi = 0x20000000 | membytes>>24;
 	msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
 	wrmsr(0x10000028, msr);
@@ -224,9 +224,9 @@ setup_gx2(void)
 #endif
 #if 0
 	msr = rdmsr(0x10000028);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
 	msr = rdmsr(0x40000029);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
 #endif
 #if 1
 	/* fixme: SMM MSR 0x10000026 and 0x400000023 */
@@ -240,7 +240,7 @@ setup_gx2(void)
 	/* calculate the PBASE and PMASK fields */
 	tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20  == left 8 */
 	tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
 	msr.hi = tmp;
 	msr.lo = tmp2;
 	wrmsr(0x10000026, msr);
@@ -251,14 +251,14 @@ setup_gx2(void)
 	msr.lo = 0x400fffc0;
 	wrmsr(0x10000026, msr);
 	msr = rdmsr(0x10000026);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
 #endif
 #if 0
 	msr.hi = 0x22fffc02;
 	msr.lo = 0x10ffbf00;
 	wrmsr(0x1808, msr);
 	msr = rdmsr(0x1808);
-	printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
 #endif
 #if 0	// SDG - don't do this
 	/* now do the default MSR values */
@@ -266,7 +266,7 @@ setup_gx2(void)
 		msr_t msr;
 		wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr);	// MSR - see table above
 		msr = rdmsr(msr_defaults[i].msr_no);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
 	}
 #endif
 }
@@ -281,7 +281,7 @@ static void northbridge_init(device_t dev)
 	unsigned long m;
 
 	struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
-	printk_debug("northbridge: %s()\n", __func__);
+	printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
 	
 	enable_shadow(dev);
 	irq_init_steering(dev, nb->irqmap);
@@ -429,10 +429,10 @@ static void pci_domain_set_resources(device_t dev)
 		*bcdramtop = ((tomk << 10) - 1);
 		*mcgbaseadd = (tomk >> 9);
 
-		printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
-		printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
+		printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
+		printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
 
-		printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
+		printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
 
 		/* Compute the top of Low memory */
 		tolmk = pci_tolm >> 10;
@@ -483,7 +483,7 @@ extern uint64_t high_tables_base, high_tables_size;
 
 static void enable_dev(struct device *dev)
 {
-	printk_debug("gx2 north: enable_dev\n");
+	printk(BIOS_DEBUG, "gx2 north: enable_dev\n");
 	void northbridgeinit(void);
 	void chipsetinit(struct northbridge_amd_gx2_config *nb);
 	void do_vsmbios(void);
@@ -492,7 +492,7 @@ static void enable_dev(struct device *dev)
 		struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
 		extern void cpubug(void);
 		u32 tomk;
-		printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
+		printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n");
 		/* cpubug MUST be called before setup_gx2(), so we force the issue here */
 		northbridgeinit();
 		cpubug();	
@@ -510,10 +510,10 @@ static void enable_dev(struct device *dev)
 #endif
 		ram_resource(dev, 0, 0, tomk);
         } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
-		printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
+		printk(BIOS_DEBUG, "DEVICE_PATH_APIC_CLUSTER\n");
                 dev->ops = &cpu_bus_ops;
         }
-	printk_debug("gx2 north: end enable_dev\n");
+	printk(BIOS_DEBUG, "gx2 north: end enable_dev\n");
 }
 
 struct chip_operations northbridge_amd_gx2_ops = {
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 995c1f3212..491466577d 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -112,10 +112,10 @@ writeglmsr(struct gliutable *gl){
 	msr.lo = gl->lo;
 	msr.hi = gl->hi;
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk_debug("%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 	/* they do this, so we do this */
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
 static void
@@ -147,7 +147,7 @@ SysmemInit(struct gliutable *gl)
 	 * system. We will adjust for SMM and DMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
-	printk_debug("%s: enable for %dm bytes\n", __func__, sizembytes);
+	printk(BIOS_DEBUG, "%s: enable for %dm bytes\n", __func__, sizembytes);
 	sizebytes = sizembytes << 20;
 
 	sizebytes -= SMM_SIZE*1024 +1;
@@ -164,7 +164,7 @@ SysmemInit(struct gliutable *gl)
 	msr.lo = sizebytes;
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, 
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, 
 				gl->desc_name, msr.hi, msr.lo);
 	
 }
@@ -177,11 +177,11 @@ DMMGL0Init(struct gliutable *gl) {
 	if (! havedmi)
 		return;
 
-	printk_debug("%s: %d bytes\n", __func__, sizebytes);
+	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
 
 	sizebytes -= DMM_SIZE*1024;
 	offset = sizebytes - DMM_OFFSET;
-	printk_debug("%s: offset is 0x%08x\n", __func__, offset);
+	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, offset);
 	offset >>= 12;
 	msr.hi = (gl->hi) | (offset << 8);
 	/* I don't think this is needed */
@@ -192,7 +192,7 @@ DMMGL0Init(struct gliutable *gl) {
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 	
 }
 static void
@@ -202,7 +202,7 @@ DMMGL1Init(struct gliutable *gl) {
 	if (! havedmi)
 		return;
 
-	printk_debug("%s:\n", __func__ );
+	printk(BIOS_DEBUG, "%s:\n", __func__ );
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
@@ -210,12 +210,12 @@ DMMGL1Init(struct gliutable *gl) {
 	msr.hi |= (DMM_OFFSET >> 24);
 	msr.lo = DMM_OFFSET << 8;
 	/* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */
-	printk_err("%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
+	printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
 	msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 static void
 SMMGL0Init(struct gliutable *gl) {
@@ -228,10 +228,10 @@ SMMGL0Init(struct gliutable *gl) {
 	if (havedmi)
 		sizebytes -= DMM_SIZE * 1024;
 
-	printk_debug("%s: %d bytes\n", __func__, sizebytes);
+	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
 
 	offset = sizebytes - SMM_OFFSET;
-	printk_debug("%s: offset is 0x%08x\n", __func__, offset);
+	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, offset);
 	offset >>= 12;
 
 	msr.hi = offset << 8;
@@ -242,12 +242,12 @@ SMMGL0Init(struct gliutable *gl) {
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 static void
 SMMGL1Init(struct gliutable *gl) {
 	msr_t msr;
-	printk_debug("%s:\n", __func__ );
+	printk(BIOS_DEBUG, "%s:\n", __func__ );
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
@@ -258,7 +258,7 @@ SMMGL1Init(struct gliutable *gl) {
 	
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
 	msr = rdmsr(gl->desc_name);
-	printk_debug("%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08x, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
 static void
@@ -350,7 +350,7 @@ static void GLPCIInit(void){
 		/* So we need a high page aligned addresss (pah) and low page aligned address (pal)
 		 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
 		 */
-		printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
+		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
 		pah = ((msr.hi &0xff) << 12) | ((msr.lo >> 20) & 0xfff);
 		/* we have the page address. Now make it a page-aligned address */
 		pah <<= 12;
@@ -359,7 +359,7 @@ static void GLPCIInit(void){
 		msr.hi =  pah;
 		msr.lo =  pal;
 		msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
-		printk_debug("GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
+		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
 		msrnum = GLPCI_RC1;
 		wrmsr(msrnum, msr);
 	}
@@ -507,10 +507,10 @@ performance:
 
 	for(i = 0; gating->msrnum != 0xffffffff; i++) {
 		msr = rdmsr(gating->msrnum);
-		printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo);
 		msr.hi |= gating->msr.hi;
 		msr.lo |= gating->msr.lo;
-		printk_debug("%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__, 
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__, 
 			gating->msrnum, msr.hi, msr.lo);
 		wrmsr(gating->msrnum, msr);	// MSR - See the table above
 		gating +=1;
@@ -526,11 +526,11 @@ GeodeLinkPriority(void){
 
 	for(i = 0; prio->msrnum != 0xffffffff; i++) {
 		msr = rdmsr(prio->msrnum);
-		printk_debug("%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
 		msr.hi |= prio->msr.hi;
 		msr.lo &= ~0xfff;
 		msr.lo |= prio->msr.lo;
-		printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__, 
+		printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__, 
 			prio->msrnum, msr.hi, msr.lo);
 		wrmsr(prio->msrnum, msr);	// MSR - See the table above
 		prio +=1;
@@ -772,7 +772,7 @@ northbridgeinit(void)
 {
 	msr_t msr;
 	int i;
-	printk_debug("Enter %s\n", __func__);
+	printk(BIOS_DEBUG, "Enter %s\n", __func__);
 
 	for(i = 0; gliutables[i]; i++)
 		GLIUInit(gliutables[i]);
@@ -803,6 +803,6 @@ northbridgeinit(void)
 	ClockGatingInit();
 	__asm__("FINIT\n");
 	/* CPUBugsFix -- called elsewhere */
-	printk_debug("Exit %s\n", __func__);
+	printk(BIOS_DEBUG, "Exit %s\n", __func__);
 }
 
diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c
index 1312d78f84..85e6a45ba0 100644
--- a/src/northbridge/amd/lx/grphinit.c
+++ b/src/northbridge/amd/lx/grphinit.c
@@ -70,7 +70,7 @@ void graphics_init(void)
 	uint16_t wClassIndex, wData, res;
 
 	/* SoftVG initialization */
-	printk_debug("Graphics init...\n");
+	printk(BIOS_DEBUG, "Graphics init...\n");
    
 	geodelx_vga_msr_init();
    
@@ -99,5 +99,5 @@ void graphics_init(void)
 	vrWrite(wClassIndex, wData);
 
 	res = vrRead(wClassIndex);
-	printk_debug("VRC_VG value: 0x%04x\n", res);
+	printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);
 }
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 935d1f2b5c..5c97649ce7 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -173,96 +173,96 @@ void print_conf(void)
 		MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
 	};
 
-	printk_debug("---------- CPU ------------\n");
+	printk(BIOS_DEBUG, "---------- CPU ------------\n");
 
 	for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(cpu_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     cpu_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- GLIU 0 ------------\n");
+	printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");
 
 	for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(gliu0_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     gliu0_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- GLIU 1 ------------\n");
+	printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");
 
 	for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(gliu1_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     gliu1_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- RCONF ------------\n");
+	printk(BIOS_DEBUG, "---------- RCONF ------------\n");
 
 	for (i = 0; rconf_msr[i] != GL_END; i++) {
 		msr = rdmsr(rconf_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- VARIA ------------\n");
+	printk(BIOS_DEBUG, "---------- VARIA ------------\n");
 	msr = rdmsr(0x51300010);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
 		     msr.lo);
 
 	msr = rdmsr(0x51400015);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
 		     msr.lo);
 
-	printk_debug("---------- DIVIL IRQ ------------\n");
+	printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");
 	msr = rdmsr(MDD_IRQM_YLOW);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
 		     msr.lo);
 	msr = rdmsr(MDD_IRQM_YHIGH);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
 		     msr.hi, msr.lo);
 	msr = rdmsr(MDD_IRQM_ZLOW);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
 		     msr.lo);
 	msr = rdmsr(MDD_IRQM_ZHIGH);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
 		     msr.hi, msr.lo);
 
-	printk_debug("---------- PCI ------------\n");
+	printk(BIOS_DEBUG, "---------- PCI ------------\n");
 
 	for (i = 0; pci_msr[i] != GL_END; i++) {
 		msr = rdmsr(pci_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- LPC/UART DMA ------------\n");
+	printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");
 
 	for (i = 0; dma_msr[i] != GL_END; i++) {
 		msr = rdmsr(dma_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- CS5536 ------------\n");
+	printk(BIOS_DEBUG, "---------- CS5536 ------------\n");
 
 	for (i = 0; cs5536_msr[i] != GL_END; i++) {
 		msr = rdmsr(cs5536_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
 			     msr.hi, msr.lo);
 	}
 
 	iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
 	iol = inl(GPIOL_EVENTS_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
 	iol = inl(GPIOL_INPUT_INVERT_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
 	iol = inl(GPIO_MAPPER_X);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
 		     iol);
 #endif				//CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
 }
@@ -278,7 +278,7 @@ int sizeram(void)
 
 	/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
 	msr = rdmsr(MC_CF07_DATA);
-	printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
 
 	/* dimm 0 */
 	dimm = msr.hi;
@@ -294,7 +294,7 @@ int sizeram(void)
 		sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
 	}
 
-	printk_debug("sizeram: sizem 0x%xMB\n", sizem);
+	printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
 	return sizem;
 }
 
@@ -306,7 +306,7 @@ static void northbridge_init(device_t dev)
 {
 	//msr_t msr;
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	enable_shadow(dev);
 	/*
@@ -317,8 +317,8 @@ static void northbridge_init(device_t dev)
 	//msr.hi |= 0x3;
 	//msr.lo |= 0x30000;
 
-	//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
-	//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
+	//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
+	//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
 }
 
 void northbridge_set_resources(struct device *dev)
@@ -340,8 +340,7 @@ void northbridge_set_resources(struct device *dev)
 		struct bus *bus;
 		bus = &dev->link[link];
 		if (bus->children) {
-			printk_debug
-			    ("my_dev_set_resources: assign_resources %d\n",
+			printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",
 			     bus);
 			assign_resources(bus);
 		}
@@ -406,7 +405,7 @@ static void pci_domain_set_resources(device_t dev)
 	u32 tomk;
 	device_t mc_dev;
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	mc_dev = dev->link[0].children;
 	if (mc_dev) {
@@ -430,7 +429,7 @@ static void pci_domain_set_resources(device_t dev)
 static void pci_domain_enable(device_t dev)
 {
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	// do this here for now -- this chip really breaks our device model
 	northbridge_init_early();
@@ -439,12 +438,12 @@ static void pci_domain_enable(device_t dev)
 
 	setup_realmode_idt();
 
-	printk_debug("Before VSA:\n");
+	printk(BIOS_DEBUG, "Before VSA:\n");
 	// print_conf();
 
 	do_vsmbios();		// do the magic stuff here, so prepare your tambourine ;)
 
-	printk_debug("After VSA:\n");
+	printk(BIOS_DEBUG, "After VSA:\n");
 	// print_conf();
 
 	graphics_init();
@@ -461,7 +460,7 @@ static struct device_operations pci_domain_ops = {
 
 static void cpu_bus_init(device_t dev)
 {
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	initialize_cpus(&dev->link[0]);
 }
@@ -480,7 +479,7 @@ static struct device_operations cpu_bus_ops = {
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew(">> Entering northbridge.c: %s with path %d\n",
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",
 		    __func__, dev->path.type);
 
 	/* Set the operations if it is a special bus type */
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index 4336e82196..54cc057383 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -107,7 +107,7 @@ static void writeglmsr(struct gliutable *gl)
 	msr.lo = gl->lo;
 	msr.hi = gl->hi;
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);	// GX3
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);	// GX3
 }
 
 static void ShadowInit(struct gliutable *gl)
@@ -131,11 +131,11 @@ static void SysmemInit(struct gliutable *gl)
 	 * system. We will adjust for SMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
-	printk_debug("%s: enable for %dMBytes\n", __func__, sizembytes);
+	printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);
 	sizebytes = sizembytes << 20;
 
 	sizebytes -= ((SMM_SIZE * 1024) + 1);
-	printk_debug("usable RAM: %d bytes\n", sizebytes);
+	printk(BIOS_DEBUG, "usable RAM: %d bytes\n", sizebytes);
 
 	/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
 	   The top 8 bits go into 0-7 of msr.hi. */
@@ -147,7 +147,7 @@ static void SysmemInit(struct gliutable *gl)
 	msr.lo = sizebytes;
 
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
@@ -159,12 +159,12 @@ static void SMMGL0Init(struct gliutable *gl)
 
 	sizebytes -= (SMM_SIZE * 1024);
 
-	printk_debug("%s: %d bytes\n", __func__, sizebytes);
+	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
 
 	/* calculate the Two's complement offset */
 	offset = sizebytes - SMM_OFFSET;
 	offset = (offset >> 12) & 0x000fffff;
-	printk_debug("%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
+	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
 
 	msr.hi = offset << 8 | gl->hi;
 	msr.hi |= SMM_OFFSET >> 24;
@@ -173,14 +173,14 @@ static void SMMGL0Init(struct gliutable *gl)
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
 static void SMMGL1Init(struct gliutable *gl)
 {
 	msr_t msr;
-	printk_debug("%s:\n", __func__);
+	printk(BIOS_DEBUG, "%s:\n", __func__);
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
@@ -190,7 +190,7 @@ static void SMMGL1Init(struct gliutable *gl)
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
@@ -290,7 +290,7 @@ static void GLPCIInit(void)
 		msr.lo |=
 		    GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET |
 		    GLPCI_RC_LOWER_WC_SET;
-		printk_debug("GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
+		printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
 			     msr.lo, msr.hi);
 		msrnum = GLPCI_RC1;
 		wrmsr(msrnum, msr);
@@ -304,7 +304,7 @@ static void GLPCIInit(void)
 	      (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
 	msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
 	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
-	printk_debug("GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,
+	printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,
 		     msr.hi);
 	msrnum = GLPCI_RC2;
 	wrmsr(msrnum, msr);
@@ -435,7 +435,7 @@ static void ClockGatingInit(void)
 		msr = rdmsr(gating->msrnum);
 		msr.hi |= gating->msr.hi;
 		msr.lo |= gating->msr.lo;
-		/* printk_debug("%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__,
+		/* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__,
 		   gating->msrnum, msr.hi, msr.lo); */// GX3
 		wrmsr(gating->msrnum, msr);	// MSR - See the table above
 		gating += 1;
@@ -454,7 +454,7 @@ static void GeodeLinkPriority(void)
 		msr.hi |= prio->msr.hi;
 		msr.lo &= ~0xfff;
 		msr.lo |= prio->msr.lo;
-		/* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,
+		/* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,
 		   prio->msrnum, msr.hi, msr.lo);  */// GX3
 		wrmsr(prio->msrnum, msr);	// MSR - See the table above
 		prio += 1;
@@ -651,7 +651,7 @@ static void enable_L1_cache(void)
 
 	// now program RCONF_DEFAULT
 	wrmsr(CPU_RCONF_DEFAULT, msr);
-	printk_debug("CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
+	printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
 		     msr.lo);
 
 	// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.
@@ -663,7 +663,7 @@ static void enable_L1_cache(void)
 	    (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
 	wrmsr(CPU_RCONF_BYPASS, msr);
 
-	printk_debug("CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,
+	printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,
 		     msr.lo);
 }
 
@@ -695,7 +695,7 @@ static void enable_L2_cache(void)
 	msr.lo = 0x0f;
 	wrmsr(CPU_BC_L2_CONF, msr);
 
-	printk_debug("L2 cache enabled\n");
+	printk(BIOS_DEBUG, "L2 cache enabled\n");
 }
 
 static void setup_lx_cache(void)
@@ -748,7 +748,7 @@ uint32_t get_systop(void)
 void northbridge_init_early(void)
 {
 	int i;
-	printk_debug("Enter %s\n", __func__);
+	printk(BIOS_DEBUG, "Enter %s\n", __func__);
 
 	for (i = 0; gliutables[i]; i++)
 		GLIUInit(gliutables[i]);
@@ -768,5 +768,5 @@ void northbridge_init_early(void)
 	ClockGatingInit();
 
 	__asm__ __volatile__("FINIT\n");
-	printk_debug("Exit %s\n", __func__);
+	printk(BIOS_DEBUG, "Exit %s\n", __func__);
 }