diff options
| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-28 03:32:23 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-28 03:32:23 +0000 |
| commit | 82b241a2b5e38046a519673264c47c64d4c85728 (patch) | |
| tree | e66acb13315f9ed2617822cc333c96e75a6f03f8 /src/northbridge/amd | |
| parent | 5bcedee0f88fa6390d84f2641dc5b3e109cf6ea3 (diff) | |
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.
Well, I understand it better like this, but maybe
it's only me, part of the changes are paranoic, and
the only effective change is for a factor depending on
mobile or not that I can't test.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
| -rw-r--r-- | src/northbridge/amd/amdht/AsPsDefs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index eefedb63ee..dd59496c49 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -25,7 +25,7 @@ #define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */ #define PS_LIM_REG 0xC0010061 /* P-state Current Limit Register */ -#define PS_CUR_LIM_SHFT 4 /* P-state Current Limit shift position */ +#define PS_MAX_VAL_SHFT 4 /* P-state Maximum Value shift position */ #define PS_CTL_REG 0xC0010062 /* P-state Control Register */ #define PS_CMD_MASK_OFF 0xfffffff8 /* P-state Control Register CMD Mask OFF */ |