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authorLi-Ta Lo <ollie@lanl.gov>2006-04-26 22:07:16 +0000
committerLi-Ta Lo <ollie@lanl.gov>2006-04-26 22:07:16 +0000
commitb7a09b4f19aa5e9d23118d32e523470e590318eb (patch)
treeb9a53ab2f4647cf59d6c2201bc22804f748a822b /src/northbridge/amd
parentae11b37ea54fc1716797a32223fc0a86aed3aab5 (diff)
some todo and comment for ron.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/gx2/northbridgeinit.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 6f638c244e..0998a6af96 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -330,16 +330,13 @@ static void GLPCIInit(void){
/* */
/* R1 - GLPCI settings for SysMem space.*/
/* */
-
/* Get systop from GLIU0 SYSTOP Descriptor*/
-
for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
if (gliu0table[i].desc_type == R_SYSMEM) {
gl = &gliu0table[i];
break;
}
}
-
if (gl) {
msrnum = gl->desc_name;
msr = rdmsr(msrnum);
@@ -373,16 +370,12 @@ static void GLPCIInit(void){
msrnum = CPU_RCONF_A0_BF;
wrmsr(msrnum, msr);
-
msrnum = CPU_RCONF_C0_DF;
wrmsr(msrnum, msr);
-
msrnum = CPU_RCONF_E0_FF;
wrmsr(msrnum, msr);
-
-
/* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup.*/
msrnum = GLPCI_A0_BF;
msr.hi = 0x35353535;
@@ -400,7 +393,6 @@ static void GLPCIInit(void){
wrmsr(msrnum, msr);
/* Set WSREQ*/
-
msrnum = CPU_DM_CONFIG0;
msr = rdmsr(msrnum);
msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);