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authorDuncan Laurie <dlaurie@chromium.org>2013-10-31 08:26:23 -0700
committerAaron Durbin <adurbin@google.com>2014-03-04 16:31:14 +0100
commit7274800ea37edf41cb50e899d03baa02bdeecade (patch)
treed49fb358ea2b46490bdf7007365ce4a3c0cb3cb7 /src/northbridge/amd
parent0567c91b22e36eb07e7c7b8a67cbf6b41778db30 (diff)
Add a generic register script handler
This is based on the RCBA configuration setup from haswell. It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF. I did not extend it to handle MSR yet but that would be another potential register type. There are a number of approaches to this kind of thing, but in the end they have a lot of switch statements and a mass of #defines. I'm not particularly set on any of the details so comments welcome. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175206 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4923 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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