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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2010-03-01 10:30:08 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-03-01 10:30:08 +0000
commit55cf7bcbeb605648ccfa2fdab102506f87388c07 (patch)
treec92cc09324c72d674692022b97e622d39a10c485 /src/northbridge/amd
parent72f75b1c8b3a5513e467cea1af745bcbd310e881 (diff)
Allow per-board setting of HT clock and width so
less than optimal PCB designs can still work reliably with reduced clock. Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5179 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd')
-rw-r--r--src/northbridge/amd/amdht/h3finit.c44
1 files changed, 43 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
index 98af59f679..be55c063bb 100644
--- a/src/northbridge/amd/amdht/h3finit.c
+++ b/src/northbridge/amd/amdht/h3finit.c
@@ -1327,9 +1327,51 @@ void selectOptimalWidthAndFrequency(sMainData *pDat)
for (i = 0; i < pDat->TotalLinks*2; i += 2)
{
- cbPCBFreqLimit = 0xFFFF;
+#if CONFIG_LIMIT_HT_SPEED_200
+ cbPCBFreqLimit = 0x0001;
+#elif CONFIG_LIMIT_HT_SPEED_300
+ cbPCBFreqLimit = 0x0003;
+#elif CONFIG_LIMIT_HT_SPEED_400
+ cbPCBFreqLimit = 0x0007;
+#elif CONFIG_LIMIT_HT_SPEED_500
+ cbPCBFreqLimit = 0x000F;
+#elif CONFIG_LIMIT_HT_SPEED_600
+ cbPCBFreqLimit = 0x001F;
+#elif CONFIG_LIMIT_HT_SPEED_800
+ cbPCBFreqLimit = 0x003F;
+#elif CONFIG_LIMIT_HT_SPEED_1000
+ cbPCBFreqLimit = 0x007F;
+#elif CONFIG_LIMIT_HT_SPEED_1200
+ cbPCBFreqLimit = 0x00FF;
+#elif CONFIG_LIMIT_HT_SPEED_1400
+ cbPCBFreqLimit = 0x01FF;
+#elif CONFIG_LIMIT_HT_SPEED_1600
+ cbPCBFreqLimit = 0x03FF;
+#elif CONFIG_LIMIT_HT_SPEED_1800
+ cbPCBFreqLimit = 0x07FF;
+#elif CONFIG_LIMIT_HT_SPEED_2000
+ cbPCBFreqLimit = 0x0FFF;
+#elif CONFIG_LIMIT_HT_SPEED_2200
+ cbPCBFreqLimit = 0x1FFF;
+#elif CONFIG_LIMIT_HT_SPEED_2400
+ cbPCBFreqLimit = 0x3FFF;
+#elif CONFIG_LIMIT_HT_SPEED_2600
+ cbPCBFreqLimit = 0x7FFF;
+#else
+ cbPCBFreqLimit = 0xFFFF; // Maximum allowed by autoconfiguration
+#endif
+
+#if CONFIG_LIMIT_HT_DOWN_WIDTH_8
+ cbPCBABDownstreamWidth = 8;
+#else
cbPCBABDownstreamWidth = 16;
+#endif
+
+#if CONFIG_LIMIT_HT_UP_WIDTH_8
+ cbPCBBAUpstreamWidth = 8;
+#else
cbPCBBAUpstreamWidth = 16;
+#endif
if ( (pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_CPU))
{