nb/amd/pi/00730F01: Initialize IOMMU device

Change-Id: I12d3ed35770ee06626f884db23004652084c88c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15186
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 63 insertions, 1 deletions

diff --git a/src/northbridge/amd/pi/00730F01/Makefile.inc b/src/northbridge/amd/pi/00730F01/Makefile.inc
index 3cf4ed1355..39c3ee61ba 100644
--- a/src/northbridge/amd/pi/00730F01/Makefile.inc
+++ b/src/northbridge/amd/pi/00730F01/Makefile.inc
@@ -16,3 +16,4 @@
 romstage-y += dimmSpd.c
 
 ramstage-y += northbridge.c
+ramstage-y += iommu.c
diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c
new file mode 100644
index 0000000000..1ff4cfbbc9
--- /dev/null
+++ b/src/northbridge/amd/pi/00730F01/iommu.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <lib.h>
+
+static void iommu_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, 0x44);
+	res->size = 512 * 1024;
+	res->align = log2(res->size);
+	res->gran = log2(res->size);
+	res->limit = 0xffffffff;	/* 4G */
+	res->flags = IORESOURCE_MEM;
+}
+
+static void iommu_set_resources(struct device *dev)
+{
+	pci_dev_set_resources(dev);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations iommu_ops = {
+	.read_resources = iommu_read_resources,
+	.set_resources = iommu_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver iommu_driver __pci_driver = {
+	.ops = &iommu_ops,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU,
+};
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 67c8a5939c..d083883eb3 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -199,7 +199,6 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
 	EnvParam->FchInterface.SataEnable = !((CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3));
 	EnvParam->FchInterface.IdeEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3);
 	EnvParam->FchInterface.SataIdeMode = (CONFIG_HUDSON_SATA_MODE == 3);
-	EnvParam->GnbEnvConfiguration.IommuSupport = FALSE;
 
 	status = AmdInitEnv (EnvParam);
 	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus);
@@ -274,6 +273,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
 	/* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
 	AmdCreateStruct(&AmdParamStruct);
 	AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
+	AmdLateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1;
+	AmdLateParams->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS;
 	Status = AmdInitLate(AmdLateParams);
 	if (Status != AGESA_SUCCESS) {
 		agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus);