diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-20 20:12:32 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-20 16:07:02 +0000 |
| commit | 113f670baabab0776e68c877fe6b3d7dd07e79a9 (patch) | |
| tree | 021969c4e70f06480911359ec5ec66f5a43bb15f /src/northbridge/amd/pi | |
| parent | 71955a5b3fff71ee56600fb4345f343187faf24b (diff) | |
AGESA binaryPI: Fix and optimize for MAX_NODES_NUM
With nodeid<8, CONFIG_CDB==0x18, PCI device number does
not overflow. CONFIG_CDB is not a value we can configure.
Change-Id: I23e9707a8ec12dcd80c00688d6237d085d1abf36
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/northbridge/amd/pi')
| -rw-r--r-- | src/northbridge/amd/pi/00630F01/northbridge.c | 17 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/00660F01/northbridge.c | 21 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/northbridge.c | 21 |
3 files changed, 5 insertions, 54 deletions
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index fed7e53c81..76ce9da056 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -44,7 +44,7 @@ #include <arch/acpigen.h> #include <assert.h> -#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) +#define MAX_NODE_NUMS MAX_NODES #if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! @@ -110,11 +110,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static struct device *get_node_pci(u32 nodeid, u32 fn) { - if (((CONFIG_CDB + nodeid) < 32) || (MAX_NODE_NUMS + CONFIG_CDB < 32)) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); - } else { - return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); - } + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } static void get_fx_devs(void) @@ -157,14 +153,7 @@ static void f1_write_config32(unsigned reg, u32 value) static u32 amdfam15_nodeid(struct device *dev) { - unsigned busn; - busn = dev->bus->secondary; - - if ((busn != CONFIG_CBB) && (MAX_NODE_NUMS == 64)) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; - } else { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; - } + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } static void set_vga_enable_reg(u32 nodeid, u32 linkn) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 39c1d9ff89..795bc61cc8 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -43,7 +43,7 @@ #include <arch/acpi.h> #include <arch/acpigen.h> -#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) +#define MAX_NODE_NUMS MAX_NODES #if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT) #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! @@ -109,15 +109,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static struct device *get_node_pci(u32 nodeid, u32 fn) { -#if MAX_NODE_NUMS + CONFIG_CDB >= 32 - if ((CONFIG_CDB + nodeid) < 32) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); - } else { - return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); - } -#else return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); -#endif } static void get_fx_devs(void) @@ -160,18 +152,7 @@ static void f1_write_config32(unsigned reg, u32 value) static u32 amdfam15_nodeid(struct device *dev) { -#if MAX_NODE_NUMS == 64 - unsigned busn; - busn = dev->bus->secondary; - if (busn != CONFIG_CBB) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; - } else { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; - } - -#else return (dev->path.pci.devfn >> 3) - CONFIG_CDB; -#endif } static void set_vga_enable_reg(u32 nodeid, u32 linkn) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 456e880bc8..db4c14bb88 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -43,7 +43,7 @@ #include <arch/acpi.h> #include <arch/acpigen.h> -#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) +#define MAX_NODE_NUMS MAX_NODES typedef struct dram_base_mask { u32 base; //[47:27] at [28:8] @@ -105,15 +105,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi static struct device *get_node_pci(u32 nodeid, u32 fn) { -#if MAX_NODE_NUMS + CONFIG_CDB >= 32 - if ((CONFIG_CDB + nodeid) < 32) { - return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); - } else { - return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); - } -#else return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); -#endif } static void get_fx_devs(void) @@ -156,18 +148,7 @@ static void f1_write_config32(unsigned reg, u32 value) static u32 amdfam16_nodeid(struct device *dev) { -#if MAX_NODE_NUMS == 64 - unsigned busn; - busn = dev->bus->secondary; - if (busn != CONFIG_CBB) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; - } else { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; - } - -#else return (dev->path.pci.devfn >> 3) - CONFIG_CDB; -#endif } static void set_vga_enable_reg(u32 nodeid, u32 linkn) |