printk_foo -> printk(BIOS_FOO, ...)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 58 insertions, 59 deletions

diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c
index 1312d78f84..85e6a45ba0 100644
--- a/src/northbridge/amd/lx/grphinit.c
+++ b/src/northbridge/amd/lx/grphinit.c
@@ -70,7 +70,7 @@ void graphics_init(void)
 	uint16_t wClassIndex, wData, res;
 
 	/* SoftVG initialization */
-	printk_debug("Graphics init...\n");
+	printk(BIOS_DEBUG, "Graphics init...\n");
    
 	geodelx_vga_msr_init();
    
@@ -99,5 +99,5 @@ void graphics_init(void)
 	vrWrite(wClassIndex, wData);
 
 	res = vrRead(wClassIndex);
-	printk_debug("VRC_VG value: 0x%04x\n", res);
+	printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);
 }
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 935d1f2b5c..5c97649ce7 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -173,96 +173,96 @@ void print_conf(void)
 		MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
 	};
 
-	printk_debug("---------- CPU ------------\n");
+	printk(BIOS_DEBUG, "---------- CPU ------------\n");
 
 	for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(cpu_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     cpu_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- GLIU 0 ------------\n");
+	printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");
 
 	for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(gliu0_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     gliu0_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- GLIU 1 ------------\n");
+	printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");
 
 	for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
 		msr = rdmsr(gliu1_msr_defs[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
 			     gliu1_msr_defs[i], msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- RCONF ------------\n");
+	printk(BIOS_DEBUG, "---------- RCONF ------------\n");
 
 	for (i = 0; rconf_msr[i] != GL_END; i++) {
 		msr = rdmsr(rconf_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- VARIA ------------\n");
+	printk(BIOS_DEBUG, "---------- VARIA ------------\n");
 	msr = rdmsr(0x51300010);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
 		     msr.lo);
 
 	msr = rdmsr(0x51400015);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
 		     msr.lo);
 
-	printk_debug("---------- DIVIL IRQ ------------\n");
+	printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");
 	msr = rdmsr(MDD_IRQM_YLOW);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
 		     msr.lo);
 	msr = rdmsr(MDD_IRQM_YHIGH);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
 		     msr.hi, msr.lo);
 	msr = rdmsr(MDD_IRQM_ZLOW);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
 		     msr.lo);
 	msr = rdmsr(MDD_IRQM_ZHIGH);
-	printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
+	printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
 		     msr.hi, msr.lo);
 
-	printk_debug("---------- PCI ------------\n");
+	printk(BIOS_DEBUG, "---------- PCI ------------\n");
 
 	for (i = 0; pci_msr[i] != GL_END; i++) {
 		msr = rdmsr(pci_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- LPC/UART DMA ------------\n");
+	printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");
 
 	for (i = 0; dma_msr[i] != GL_END; i++) {
 		msr = rdmsr(dma_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
 			     msr.hi, msr.lo);
 	}
 
-	printk_debug("---------- CS5536 ------------\n");
+	printk(BIOS_DEBUG, "---------- CS5536 ------------\n");
 
 	for (i = 0; cs5536_msr[i] != GL_END; i++) {
 		msr = rdmsr(cs5536_msr[i]);
-		printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
+		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
 			     msr.hi, msr.lo);
 	}
 
 	iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
 	iol = inl(GPIOL_EVENTS_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
 	iol = inl(GPIOL_INPUT_INVERT_ENABLE);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n",
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
 		     GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
 	iol = inl(GPIO_MAPPER_X);
-	printk_debug("IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
+	printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
 		     iol);
 #endif				//CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
 }
@@ -278,7 +278,7 @@ int sizeram(void)
 
 	/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
 	msr = rdmsr(MC_CF07_DATA);
-	printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
+	printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
 
 	/* dimm 0 */
 	dimm = msr.hi;
@@ -294,7 +294,7 @@ int sizeram(void)
 		sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
 	}
 
-	printk_debug("sizeram: sizem 0x%xMB\n", sizem);
+	printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
 	return sizem;
 }
 
@@ -306,7 +306,7 @@ static void northbridge_init(device_t dev)
 {
 	//msr_t msr;
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	enable_shadow(dev);
 	/*
@@ -317,8 +317,8 @@ static void northbridge_init(device_t dev)
 	//msr.hi |= 0x3;
 	//msr.lo |= 0x30000;
 
-	//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
-	//printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
+	//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
+	//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
 }
 
 void northbridge_set_resources(struct device *dev)
@@ -340,8 +340,7 @@ void northbridge_set_resources(struct device *dev)
 		struct bus *bus;
 		bus = &dev->link[link];
 		if (bus->children) {
-			printk_debug
-			    ("my_dev_set_resources: assign_resources %d\n",
+			printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",
 			     bus);
 			assign_resources(bus);
 		}
@@ -406,7 +405,7 @@ static void pci_domain_set_resources(device_t dev)
 	u32 tomk;
 	device_t mc_dev;
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	mc_dev = dev->link[0].children;
 	if (mc_dev) {
@@ -430,7 +429,7 @@ static void pci_domain_set_resources(device_t dev)
 static void pci_domain_enable(device_t dev)
 {
 
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	// do this here for now -- this chip really breaks our device model
 	northbridge_init_early();
@@ -439,12 +438,12 @@ static void pci_domain_enable(device_t dev)
 
 	setup_realmode_idt();
 
-	printk_debug("Before VSA:\n");
+	printk(BIOS_DEBUG, "Before VSA:\n");
 	// print_conf();
 
 	do_vsmbios();		// do the magic stuff here, so prepare your tambourine ;)
 
-	printk_debug("After VSA:\n");
+	printk(BIOS_DEBUG, "After VSA:\n");
 	// print_conf();
 
 	graphics_init();
@@ -461,7 +460,7 @@ static struct device_operations pci_domain_ops = {
 
 static void cpu_bus_init(device_t dev)
 {
-	printk_spew(">> Entering northbridge.c: %s\n", __func__);
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
 
 	initialize_cpus(&dev->link[0]);
 }
@@ -480,7 +479,7 @@ static struct device_operations cpu_bus_ops = {
 
 static void enable_dev(struct device *dev)
 {
-	printk_spew(">> Entering northbridge.c: %s with path %d\n",
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",
 		    __func__, dev->path.type);
 
 	/* Set the operations if it is a special bus type */
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index 4336e82196..54cc057383 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -107,7 +107,7 @@ static void writeglmsr(struct gliutable *gl)
 	msr.lo = gl->lo;
 	msr.hi = gl->hi;
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);	// GX3
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);	// GX3
 }
 
 static void ShadowInit(struct gliutable *gl)
@@ -131,11 +131,11 @@ static void SysmemInit(struct gliutable *gl)
 	 * system. We will adjust for SMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
-	printk_debug("%s: enable for %dMBytes\n", __func__, sizembytes);
+	printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);
 	sizebytes = sizembytes << 20;
 
 	sizebytes -= ((SMM_SIZE * 1024) + 1);
-	printk_debug("usable RAM: %d bytes\n", sizebytes);
+	printk(BIOS_DEBUG, "usable RAM: %d bytes\n", sizebytes);
 
 	/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
 	   The top 8 bits go into 0-7 of msr.hi. */
@@ -147,7 +147,7 @@ static void SysmemInit(struct gliutable *gl)
 	msr.lo = sizebytes;
 
 	wrmsr(gl->desc_name, msr);	// MSR - see table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
@@ -159,12 +159,12 @@ static void SMMGL0Init(struct gliutable *gl)
 
 	sizebytes -= (SMM_SIZE * 1024);
 
-	printk_debug("%s: %d bytes\n", __func__, sizebytes);
+	printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
 
 	/* calculate the Two's complement offset */
 	offset = sizebytes - SMM_OFFSET;
 	offset = (offset >> 12) & 0x000fffff;
-	printk_debug("%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
+	printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
 
 	msr.hi = offset << 8 | gl->hi;
 	msr.hi |= SMM_OFFSET >> 24;
@@ -173,14 +173,14 @@ static void SMMGL0Init(struct gliutable *gl)
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
 static void SMMGL1Init(struct gliutable *gl)
 {
 	msr_t msr;
-	printk_debug("%s:\n", __func__);
+	printk(BIOS_DEBUG, "%s:\n", __func__);
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
@@ -190,7 +190,7 @@ static void SMMGL1Init(struct gliutable *gl)
 	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
 
 	wrmsr(gl->desc_name, msr);	// MSR - See table above
-	printk_debug("%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
+	printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
 		     gl->desc_name, msr.hi, msr.lo);
 }
 
@@ -290,7 +290,7 @@ static void GLPCIInit(void)
 		msr.lo |=
 		    GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET |
 		    GLPCI_RC_LOWER_WC_SET;
-		printk_debug("GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
+		printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n",
 			     msr.lo, msr.hi);
 		msrnum = GLPCI_RC1;
 		wrmsr(msrnum, msr);
@@ -304,7 +304,7 @@ static void GLPCIInit(void)
 	      (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
 	msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
 	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
-	printk_debug("GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,
+	printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo,
 		     msr.hi);
 	msrnum = GLPCI_RC2;
 	wrmsr(msrnum, msr);
@@ -435,7 +435,7 @@ static void ClockGatingInit(void)
 		msr = rdmsr(gating->msrnum);
 		msr.hi |= gating->msr.hi;
 		msr.lo |= gating->msr.lo;
-		/* printk_debug("%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__,
+		/* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to  0x%08x:0x%08x\n", __func__,
 		   gating->msrnum, msr.hi, msr.lo); */// GX3
 		wrmsr(gating->msrnum, msr);	// MSR - See the table above
 		gating += 1;
@@ -454,7 +454,7 @@ static void GeodeLinkPriority(void)
 		msr.hi |= prio->msr.hi;
 		msr.lo &= ~0xfff;
 		msr.lo |= prio->msr.lo;
-		/* printk_debug("%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,
+		/* printk(BIOS_DEBUG, "%s: MSR 0x%08x will be set to 0x%08x:0x%08x\n", __func__,
 		   prio->msrnum, msr.hi, msr.lo);  */// GX3
 		wrmsr(prio->msrnum, msr);	// MSR - See the table above
 		prio += 1;
@@ -651,7 +651,7 @@ static void enable_L1_cache(void)
 
 	// now program RCONF_DEFAULT
 	wrmsr(CPU_RCONF_DEFAULT, msr);
-	printk_debug("CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
+	printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi,
 		     msr.lo);
 
 	// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.
@@ -663,7 +663,7 @@ static void enable_L1_cache(void)
 	    (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
 	wrmsr(CPU_RCONF_BYPASS, msr);
 
-	printk_debug("CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,
+	printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi,
 		     msr.lo);
 }
 
@@ -695,7 +695,7 @@ static void enable_L2_cache(void)
 	msr.lo = 0x0f;
 	wrmsr(CPU_BC_L2_CONF, msr);
 
-	printk_debug("L2 cache enabled\n");
+	printk(BIOS_DEBUG, "L2 cache enabled\n");
 }
 
 static void setup_lx_cache(void)
@@ -748,7 +748,7 @@ uint32_t get_systop(void)
 void northbridge_init_early(void)
 {
 	int i;
-	printk_debug("Enter %s\n", __func__);
+	printk(BIOS_DEBUG, "Enter %s\n", __func__);
 
 	for (i = 0; gliutables[i]; i++)
 		GLIUInit(gliutables[i]);
@@ -768,5 +768,5 @@ void northbridge_init_early(void)
 	ClockGatingInit();
 
 	__asm__ __volatile__("FINIT\n");
-	printk_debug("Exit %s\n", __func__);
+	printk(BIOS_DEBUG, "Exit %s\n", __func__);
 }