diff options
| author | Ron Minnich <Ron Minnich> | 2006-07-28 16:06:16 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-07-28 16:06:16 +0000 |
| commit | 5e9dc231209c1a293b5a92a9ea78eb07ce0a3086 (patch) | |
| tree | 00c90e50087fba91bf5fb2cab050b3191b1daf46 /src/northbridge/amd/lx/pll_reset.c | |
| parent | e534daa05ae7057ad615e15fa3021b19f4850fd0 (diff) | |
This patch adds support for the AMD LX cpu.
There is one global change to pci_ids.h. The rest are changes for LX. I
ran abuild and it is ok. Not all artec design changes are included as
some of them would adversely affect other mainboards. Indrek will need
to test.
Signed-off-by: Ron Minnich
Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec
design.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/lx/pll_reset.c')
| -rw-r--r-- | src/northbridge/amd/lx/pll_reset.c | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c new file mode 100644 index 0000000000..be92e9b90d --- /dev/null +++ b/src/northbridge/amd/lx/pll_reset.c @@ -0,0 +1,85 @@ +#define POST_CODE(x) outb(0x80, x) + +static void pll_reset(void) +{ + msr_t msrGlcpSysRstpll; + + msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); + + print_debug("MSR GLCP_SYS_RSTPLL ("); + print_debug_hex32(GLCP_SYS_RSTPLL); + print_debug(") value is: "); + print_debug_hex32(msrGlcpSysRstpll.hi); + print_debug(":"); + print_debug_hex32(msrGlcpSysRstpll.lo); + print_debug("\n"); + + msrGlcpSysRstpll.lo &= 0x80000000; + + // If the "we've already been here" flag is set, don't reconfigure the pll + if ( !(msrGlcpSysRstpll.lo) ) + { // we haven't configured the PLL; do it now + POST_CODE(0x77); + + /* + * 64 - 32 | 31-0 + * + * (03FB) + * 0000 0011 1111 1011 | 1000 0000 1101 1110 0000 0000 1000 0001 + * + * (039C) + * 0000 0011 1001 1100 | 1000 0000 1101 1110 0000 0000 1000 0001 + * + * (029C) + * 0000 0010 1001 1100 | 1000 0000 1101 1110 0000 0000 1000 0001 + * + * (02CB) + * 0000 0010 1100 1011 | 1000 0000 1101 1110 0000 0000 1000 0001 + * + * 00101 1 00101 1 | 100000 0 0 11011110 0000 0000 1000 0001 + * GLIUMULT GLIUDIV COREMULT COREDIV | SWFLAGS (RO) (RO) HOLD_COUNT + */ + + /* ### 02CB ### + * GLIUMULT = 6 + * GLIUDIV = 2 + * COREMULT = 6 + * COREDIV = 2 + * + * ### 03FB ### + * GLIUMULT = 8 + * GLIUDIV = 2 + * COREMULT = 30 + * COREDIV = 2 + * + * ### 039C ### bad... why? + * GLIUMULT = 8 + * GLIUDIV = 0 + * COREMULT = 15 + * COREDIV = 0 + * + * ### 029C ### good... + * GLIUMULT = 6 + * GLIUDIV = 0 + * COREMULT = 15 + * COREDIV = 0 + * + * CLOCK = 33 MHz + * + */ + + /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ + msrGlcpSysRstpll.hi = 0x0000029C; + + /* Hold Count - how long we will sit in reset */ + msrGlcpSysRstpll.lo = 0x00DE0000; + + /* Use SWFLAGS to remember: "we've already been here" */ + msrGlcpSysRstpll.lo |= 0x80000000; + + /* "reset the chip" value */ + msrGlcpSysRstpll.lo |= 0x00000001; + + wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); + } +} |