diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-05 18:40:51 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-09 21:31:11 +0200 |
| commit | 1a77fd3e369d9330b9abf04ac6b0d804a11e1e3e (patch) | |
| tree | f5b9eddc127701bf2f3e596224dce9dd81ec19b1 /src/northbridge/amd/lx/pll_reset.c | |
| parent | e809dd3a84a7ea07cec0dc4acedd73f50363661f (diff) | |
northbridge/amd/lx: Remove commented code
Change-Id: I37c1674ee380936aba797e24897593fcca3b0269
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16891
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/lx/pll_reset.c')
| -rw-r--r-- | src/northbridge/amd/lx/pll_reset.c | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 318c7a1be0..d98a8ea1b6 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -65,21 +65,6 @@ static void pll_reset(void) return; } -#if 0 // Unused -static unsigned int CPUSpeed(void) -{ - unsigned int speed; - msr_t msr; - - msr = rdmsr(GLCP_SYS_RSTPLL); - speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10; - if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) { - ++speed; - } - return (speed); -} -#endif - unsigned int GeodeLinkSpeed(void) { unsigned int speed; @@ -92,17 +77,3 @@ unsigned int GeodeLinkSpeed(void) } return (speed); } - -#if 0 // Unused -static unsigned int PCISpeed(void) -{ - msr_t msr; - - msr = rdmsr(GLCP_SYS_RSTPLL); - if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) { - return (66); - } else { - return (33); - } -} -#endif |