diff options
| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-03-20 20:49:34 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-03-20 20:49:34 +0000 |
| commit | db44be9405ae4b62b525fb7dad80e20c499cc07b (patch) | |
| tree | 22e6803c543d7cd9fe12fc73ae00977c9e30f6ea /src/northbridge/amd/gx2 | |
| parent | 1293041db08ab9c4a1c80096d76cd1d71e52feae (diff) | |
added definitions. added cpubug support. added object. Commented out
msr set in northbridge that conflicted with the cpubug support.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/gx2')
| -rw-r--r-- | src/northbridge/amd/gx2/northbridge.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 40aaa44a62..d2e52c4f32 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -96,7 +96,8 @@ struct msr_defaults { /* for 180a, for now, we assume VSM will configure it */ /* 180b is left at reset value,a0000-bffff is non-cacheable */ /* 180c, c0000-dffff is set to write serialize and non-cachable */ - {0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, + /* oops, 180c will be set by cpu bug handling in cpubug.c */ + //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, /* 180d is left at default, e0000-fffff is non-cached */ /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ |