diff options
| author | Li-Ta Lo <ollie@lanl.gov> | 2006-03-17 20:11:38 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2006-03-17 20:11:38 +0000 |
| commit | 042f0430d3905786620b3e74ffb8d48ea551b20c (patch) | |
| tree | 5782f93631808b9c19adc4a457e527895cfe13f6 /src/northbridge/amd/gx2/raminit.c | |
| parent | a5ce2341ec04f333297cef729892cf886710ea89 (diff) | |
resolving conflict with Ron's work
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/gx2/raminit.c')
| -rw-r--r-- | src/northbridge/amd/gx2/raminit.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index a2cc474a3a..f0156c3183 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -4,7 +4,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl) { } +#if 0 +static void sdram_set_spd_registers(const struct mem_controller *ctrl) +{ + msr_t mst; + unsigned char val; + + /* get module banks per dimm, SPD byte 5 */ + val = spd_read_byte(0xA0, 5); + if (val < 1 || val > 2) + print_err("Module banks per dimm"); +} +#endif /* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */ static void sdram_enable(int controllers, const struct mem_controller *ctrl) |