diff options
| author | Li-Ta Lo <ollie@lanl.gov> | 2006-04-13 17:00:38 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2006-04-13 17:00:38 +0000 |
| commit | d8d8fffa0edc8b86f1efab2f3a44c9d53cefe556 (patch) | |
| tree | 7ac60db80a99217f17f7148c7a93490054dbe0ac /src/northbridge/amd/gx2/northbridge.c | |
| parent | cf648c9a99c59f25400f198b99de2f92e57db349 (diff) | |
minor modification
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/gx2/northbridge.c')
| -rw-r--r-- | src/northbridge/amd/gx2/northbridge.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index af3fe7873f..7c3cb52623 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -102,10 +102,10 @@ struct msr_defaults { /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ /* we will not set 0x180f, the DMM,yet */ - {0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, - {0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, - {0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, - {0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, + //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}}, + //{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}}, + //{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}}, + //{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}}, /* now for GLPCI routing */ /* GLIU0 */ P2D_BM(0x10000020, 0x1, 0x0, 0x0, 0xfff80), @@ -424,6 +424,7 @@ static void enable_dev(struct device *dev) extern void cpubug(void); printk_debug("DEVICE_PATH_PCI_DOMAIN\n"); /* cpubug MUST be called before setup_gx2(), so we force the issue here */ + northbridgeinit(); cpubug(); chipsetinit(); setup_gx2(); |