diff options
| author | Li-Ta Lo <ollie@lanl.gov> | 2006-04-13 17:00:38 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2006-04-13 17:00:38 +0000 |
| commit | d8d8fffa0edc8b86f1efab2f3a44c9d53cefe556 (patch) | |
| tree | 7ac60db80a99217f17f7148c7a93490054dbe0ac /src/northbridge/amd/gx2/chipsetinit.c | |
| parent | cf648c9a99c59f25400f198b99de2f92e57db349 (diff) | |
minor modification
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/gx2/chipsetinit.c')
| -rw-r--r-- | src/northbridge/amd/gx2/chipsetinit.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c index 3d1f6ce4c1..2a1688a014 100644 --- a/src/northbridge/amd/gx2/chipsetinit.c +++ b/src/northbridge/amd/gx2/chipsetinit.c @@ -211,6 +211,7 @@ chipsetinit (void){ outb( P80_CHIPSET_INIT, 0x80); ChipsetGeodeLinkInit(); +#if 0 /* we hope NEVER to be in linuxbios when S3 resumes if (! IsS3Resume()) */ { @@ -227,6 +228,7 @@ chipsetinit (void){ pmChipsetInit(); } +#endif /* for later ... if 5536 set_usb_20(); */ @@ -250,7 +252,7 @@ chipsetinit (void){ msr.lo &= ~0x100; wrmsr(msrnum, msr); -/* Enable Post Primary IDE.*/ + /* Enable Post Primary IDE.*/ msrnum = GLPCI_SB_CTRL; msr = rdmsr(msrnum); msr.lo |= GLPCI_CRTL_PPIDE_SET; |