diff options
author | Ronald G. Minnich <rminnich@gmail.com> | 2006-06-10 22:57:15 +0000 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-06-10 22:57:15 +0000 |
commit | fb937496428272c5bc9001d98fb99a70961f7df4 (patch) | |
tree | b3185771903cc9c00fd38d87ab9f87698c2f42d3 /src/northbridge/amd/gx2/chipsetinit.c | |
parent | 890ee09a3224f1cfc832f7c8f03e6c2f076aeb20 (diff) |
changes from AMD for making OLPC video work.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/gx2/chipsetinit.c')
-rw-r--r-- | src/northbridge/amd/gx2/chipsetinit.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/northbridge/amd/gx2/chipsetinit.c b/src/northbridge/amd/gx2/chipsetinit.c index 2a1688a014..a149d626ef 100644 --- a/src/northbridge/amd/gx2/chipsetinit.c +++ b/src/northbridge/amd/gx2/chipsetinit.c @@ -53,7 +53,7 @@ struct msrinit CS5536_CLOCK_GATING_TABLE[] = { { GLIU_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, { GLPCI_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, { GLCP_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - { MDD_SB_GLD_MSR_PM, {.hi=0,.lo=0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977)*/ + { MDD_SB_GLD_MSR_PM, {.hi=0,.lo=0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977)*/ { ATA_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, { AC97_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, {0,{0,0}} @@ -210,7 +210,6 @@ chipsetinit (void){ outb( P80_CHIPSET_INIT, 0x80); ChipsetGeodeLinkInit(); - #if 0 /* we hope NEVER to be in linuxbios when S3 resumes if (! IsS3Resume()) */ @@ -230,16 +229,17 @@ chipsetinit (void){ } #endif - /* for later ... if 5536 set_usb_20(); */ - - /* Setup USB. Need more details. #118.18*/ - msrnum = MSR_SB_USB1 + 8; - msr.lo = 0x00012090; - msr.hi = 0; - wrmsr(msrnum, msr); - msrnum = MSR_SB_USB2 + 8; - wrmsr(msrnum, msr); + if (!is_5536()) { + /* Setup USB. Need more details. #118.18*/ + msrnum = MSR_SB_USB1 + 8; + msr.lo = 0x00012090; + msr.hi = 0; + wrmsr(msrnum, msr); + msrnum = MSR_SB_USB2 + 8; + wrmsr(msrnum, msr); + } + /* set hd IRQ */ outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE); outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT); @@ -270,7 +270,7 @@ chipsetinit (void){ for(; csi->msrnum; csi++){ msr.lo = csi->msr.lo; msr.hi = csi->msr.hi; - wrmsr(csi->msrnum, msr); + wrmsr(csi->msrnum, msr); // MSR - see table above } @@ -288,12 +288,12 @@ chipsetinit (void){ if (is_5536()) csi = CS5536_CLOCK_GATING_TABLE; else - csi = CS5535_CLOCK_GATING_TABLE; + csi = CS5535_CLOCK_GATING_TABLE; for(; csi->msrnum; csi++){ msr.lo = csi->msr.lo; msr.hi = csi->msr.hi; - wrmsr(csi->msrnum, msr); + wrmsr(csi->msrnum, msr); // MSR - see table above } } |