diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-10-20 21:32:09 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-11-15 02:59:44 +0100 |
| commit | 9597790571ce8d0e86921c3c7d1011fec8ce8a50 (patch) | |
| tree | c0f5ab3e0b6a7fee320f6dab887356fd6ee5c5ea /src/northbridge/amd/amdmct | |
| parent | 21be0d2bd03de7f914247fa56013181ea6c342f8 (diff) | |
northbridge/amd/amdmct: Reduce maximum number of DDR3 DIMMs
CAR space on certain platforms is nearly full. This prevents the
addition of necessary RAM initialization features such as x4 DIMM
support. As the DIMM SPD cache uses a sizeable amount of CAR RAM,
reducing it would free up a significant amount of CAR RAM.
DDR3-based AMD platforms only support up to 3 physical DIMMs on
each channel (6 per node). Reduce the maximum number of DIMMs
on a node from 8 to 6 accordingly.
Change-Id: I38def86da76fc622785318c825670209b2ac9017
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12107
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/amdmct')
| -rw-r--r-- | src/northbridge/amd/amdmct/wrappers/mcti.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index 762ef11f44..92979ab232 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -47,7 +47,11 @@ UPDATE AS NEEDED #endif #ifndef MAX_DIMMS_SUPPORTED -#define MAX_DIMMS_SUPPORTED 8 +#if IS_ENABLED(CONFIG_DIMM_DDR3) + #define MAX_DIMMS_SUPPORTED 6 +#else + #define MAX_DIMMS_SUPPORTED 8 +#endif #endif #ifndef MAX_CS_SUPPORTED |