northbridge/amd/amdfam10: Collect DIMM information for ramstage use

1.) Allow MCT information structures to be copied to cbmem.
2.) Retrieve DIMM vendor, model, and serial information.
3.) Allow maximum installable memory to be set via devicetree.

Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9137
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

4 files changed, 110 insertions, 4 deletions

diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index bf832dad81..64cb1bcf21 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -2122,7 +2122,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 	 * DATABload=number of ranks on the "B" bus slots.
 	 */
 
-	u16 i, j;
+	u16 i, j, k;
 	u8 smbaddr, Index;
 	u16 Checksum;
 	u8 SPDCtrl;
@@ -2183,10 +2183,34 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 								pDCTstat->DIMMValid |= 1 << i;
 						}
 					}
+					/* Get module information for SMBIOS */
+					if (pDCTstat->DIMMValid & (1 << i)) {
+						pDCTstat->DimmManufacturerID[i] = 0;
+						for (k = 0; k < 8; k++)
+							pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8);
+						for (k = 0; k < SPD_PARTN_LENGTH; k++)
+							pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k);
+						pDCTstat->DimmRevisionNumber[i] = 0;
+						for (k = 0; k < 2; k++)
+							pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8);
+						pDCTstat->DimmSerialNumber[i] = 0;
+						for (k = 0; k < 4; k++)
+							pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8);
+						pDCTstat->DimmRows[i] = mctRead_SPD(smbaddr, SPD_ROWSZ) & 0xf;
+						pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_COLSZ) & 0xf;
+						pDCTstat->DimmRanks[i] = (mctRead_SPD(smbaddr, SPD_DMBANKS) & 0x7) + 1;
+						pDCTstat->DimmBanks[i] = mctRead_SPD(smbaddr, SPD_LBANKS);
+						pDCTstat->DimmWidth[i] = mctRead_SPD(smbaddr, SPD_DEVWIDTH);
+					}
 					/* Check module type */
 					byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE);
-					if (byte & JED_REGADCMSK)
+					if (byte & JED_REGADCMSK) {
 						RegDIMMPresent |= 1 << i;
+						pDCTstat->DimmRegistered[i] = 1;
+					}
+					else {
+						pDCTstat->DimmRegistered[i] = 0;
+					}
 					/* Check ECC capable */
 					byte = mctRead_SPD(smbaddr, SPD_EDCTYPE);
 					if (byte & JED_ECC) {
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
index 0c6df6c25e..a1786965d3 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d.h
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
  * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -231,10 +232,17 @@
 #define SPD_TRC	41
 #define SPD_TRFC	42
 
+#define SPD_MANID_START		64
+#define SPD_PARTN_START		73
+#define SPD_PARTN_LENGTH	18
+#define SPD_REVNO_START		91
+
 #define SPD_MANDATEYR	93		/*Module Manufacturing Year (BCD)*/
 
 #define SPD_MANDATEWK	94		/*Module Manufacturing Week (BCD)*/
 
+#define SPD_SERIAL_START	95
+
 /*-----------------------------
 	Jedec DDR II related equates
 -----------------------------*/
@@ -512,6 +520,18 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u32 dev_map;
 	u32 dev_dct;
 	u32 dev_nbmisc;
+
+	uint8_t DimmRows[MAX_DIMMS_SUPPORTED];
+	uint8_t DimmCols[MAX_DIMMS_SUPPORTED];
+	uint8_t DimmRanks[MAX_DIMMS_SUPPORTED];
+	uint8_t DimmBanks[MAX_DIMMS_SUPPORTED];
+	uint8_t DimmWidth[MAX_DIMMS_SUPPORTED];
+	uint8_t DimmRegistered[MAX_DIMMS_SUPPORTED];
+
+	uint64_t DimmManufacturerID[MAX_DIMMS_SUPPORTED];
+	char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH];
+	uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED];
+	uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED];
 } __attribute__((packed));
 
 /*===============================================================================
@@ -666,6 +686,15 @@ struct DCTStatStruc {		/* A per Node structure*/
 					xx0b = disable
 					yy1b = enable with DctSelIntLvAddr set to yyb */
 
+/*===============================================================================
+	CBMEM storage
+===============================================================================*/
+struct amdmct_memory_info {
+	struct MCTStatStruc mct_stat;
+	struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED];
+	uint16_t ecc_enabled;
+	uint16_t ecc_scrub_rate;
+} __attribute__((packed));
 
 u32 Get_NB32(u32 dev, u32 reg);
 void Set_NB32(u32 dev, u32 reg, u32 val);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 770b663fe9..0f4dd43642 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -2030,7 +2031,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 	 * DATAAload=number of ranks on the "A" bus slots.
 	 * DATABload=number of ranks on the "B" bus slots.
 	 */
-	u16 i, j;
+	u16 i, j, k;
 	u8 smbaddr;
 	u8 SPDCtrl;
 	u16 RegDIMMPresent, MaxDimms;
@@ -2077,10 +2078,34 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
 							pDCTstat->DIMMValid |= 1 << i;
 					}
 				}
+				/* Get module information for SMBIOS */
+				if (pDCTstat->DIMMValid & (1 << i)) {
+					pDCTstat->DimmManufacturerID[i] = 0;
+					for (k = 0; k < 8; k++)
+						pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8);
+					for (k = 0; k < SPD_PARTN_LENGTH; k++)
+						pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k);
+					pDCTstat->DimmRevisionNumber[i] = 0;
+					for (k = 0; k < 2; k++)
+						pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8);
+					pDCTstat->DimmSerialNumber[i] = 0;
+					for (k = 0; k < 4; k++)
+						pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8);
+					pDCTstat->DimmRows[i] = (mctRead_SPD(smbaddr, SPD_Addressing) & 0x38) >> 3;
+					pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_Addressing) & 0x7;
+					pDCTstat->DimmRanks[i] = ((mctRead_SPD(smbaddr, SPD_Organization) & 0x38) >> 3) + 1;
+					pDCTstat->DimmBanks[i] = 1ULL << (((mctRead_SPD(smbaddr, SPD_Density) & 0x70) >> 4) + 3);
+					pDCTstat->DimmWidth[i] = 1ULL << ((mctRead_SPD(smbaddr, SPD_BusWidth) & 0x7) + 3);
+				}
 				/* Check module type */
 				byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE) & 0x7;
-				if (byte == JED_RDIMM || byte == JED_MiniRDIMM)
+				if (byte == JED_RDIMM || byte == JED_MiniRDIMM) {
 					RegDIMMPresent |= 1 << i;
+					pDCTstat->DimmRegistered[i] = 1;
+				}
+				else {
+					pDCTstat->DimmRegistered[i] = 0;
+				}
 				/* Check ECC capable */
 				byte = mctRead_SPD(smbaddr, SPD_BusWidth);
 				if (byte & JED_ECC) {
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index 8e73afe509..0b1d48fcc3 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -262,6 +263,12 @@
 
 #define SPD_MANDATEWK	94		/*Module Manufacturing Week (BCD)*/
 
+#define SPD_MANID_START		117
+#define SPD_SERIAL_START	122
+#define SPD_PARTN_START		128
+#define SPD_PARTN_LENGTH	18
+#define SPD_REVNO_START		146
+
 /*-----------------------------
 	Jedec DDR II related equates
 -----------------------------*/
@@ -575,6 +582,18 @@ struct DCTStatStruc {		/* A per Node structure*/
 	struct _sMCTStruct s_C_MCTPtr;
 	struct _sDCTStruct s_C_DCTPtr[2];
 	/* struct _sDCTStruct s_C_DCT1Ptr[8]; */
+
+	uint8_t DimmRows[MAX_DIMMS_SUPPORTED];
+	uint8_t DimmCols[MAX_DIMMS_SUPPORTED];
+	uint8_t DimmRanks[MAX_DIMMS_SUPPORTED];
+	uint8_t DimmBanks[MAX_DIMMS_SUPPORTED];
+	uint8_t DimmWidth[MAX_DIMMS_SUPPORTED];
+	uint8_t DimmRegistered[MAX_DIMMS_SUPPORTED];
+
+	uint64_t DimmManufacturerID[MAX_DIMMS_SUPPORTED];
+	char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH];
+	uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED];
+	uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED];
 } __attribute__((packed));
 
 /*===============================================================================
@@ -727,6 +746,15 @@ struct DCTStatStruc {		/* A per Node structure*/
 					xx0b = disable
 					yy1b = enable with DctSelIntLvAddr set to yyb */
 
+/*===============================================================================
+        CBMEM storage
+===============================================================================*/
+struct amdmct_memory_info {
+	struct MCTStatStruc mct_stat;
+	struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED];
+	uint16_t ecc_enabled;
+	uint16_t ecc_scrub_rate;
+} __attribute__((packed));
 
 u32 Get_NB32(u32 dev, u32 reg);
 void Set_NB32(u32 dev, u32 reg, u32 val);