diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-23 21:36:02 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:28:51 +0200 |
| commit | 5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9 (patch) | |
| tree | 8d51ad99d2d9469f195694b29a571facf18d89f8 /src/northbridge/amd/amdmct | |
| parent | 2b010b8795de84b6753c5e49d6a73c25fee96da1 (diff) | |
northbridge/amd: Add required space before opening parenthesis '('
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct')
30 files changed, 320 insertions, 320 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 0914065d2a..16e67dfdf2 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -925,7 +925,7 @@ static void ClearDCT_D(struct MCTStatStruc *pMCTstat, reg_end = 0xA4 + 0x100 * dct; } - while(reg < reg_end) { + while (reg < reg_end) { Set_NB32(dev, reg, val); reg += 4; } @@ -1694,7 +1694,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, p = Tab_S1CLKDis; dword = 0; - while(dword < MAX_DIMMS_SUPPORTED) { + while (dword < MAX_DIMMS_SUPPORTED) { val = p[dword]; print_tx("DramTimingLo: val=", val); if (!(pDCTstat->DIMMValid & (1<<val))) @@ -3518,7 +3518,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat, static void WaitRoutine_D(u32 time) { - while(time) { + while (time) { _EXECFENCE; time--; } @@ -3877,7 +3877,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, addr = HWCR; _RDMSR(addr, &lo, &hi); - if(lo & (1<<17)) { /* save the old value */ + if (lo & (1<<17)) { /* save the old value */ wrap32dis = 1; } lo |= (1<<17); /* HWCR.wrap32dis */ @@ -3906,7 +3906,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, } } } - if(!wrap32dis) { + if (!wrap32dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index 68b6bc2ea8..fd39b38170 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -61,8 +61,8 @@ static u32 bsr(u32 x) u8 i; u32 ret = 0; - for(i=31; i>0; i--) { - if(x & (1<<i)) { + for (i=31; i>0; i--) { + if (x & (1<<i)) { ret = i; break; } @@ -78,8 +78,8 @@ static u32 bsf(u32 x) u8 i; u32 ret = 32; - for(i=0; i<32; i++) { - if(x & (1<<i)) { + for (i=0; i<32; i++) { + if (x & (1<<i)) { ret = i; break; } @@ -343,7 +343,7 @@ static u32 stream_to_int(u8 const *p) val = 0; - for(i=3; i>=0; i--) { + for (i=3; i>=0; i--) { val <<= 8; valx = *(p+i); val |= valx; diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c index dbc377cea3..327acbc250 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ b/src/northbridge/amd/amdmct/mct/mctardk3.c @@ -31,7 +31,7 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct])); - if(pDCTstat->MAdimms[dct] == 1) + if (pDCTstat->MAdimms[dct] == 1) pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 75ohms */ else pDCTstat->CH_ODC_CTL[dct] |= 0x10000000; /* 150ohms */ @@ -176,7 +176,7 @@ static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, *AddrTmgCTL = 0; *ODC_CTL = 0; - if(mctGet_NVbits(NV_MAX_DIMMS) == 8) { + if (mctGet_NVbits(NV_MAX_DIMMS) == 8) { /* 8 DIMM Table */ p = Table_ATC_ODC_8D_D; //FIXME Add Ax support @@ -188,8 +188,8 @@ static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, while (*p != 0xFF) { if ((MAAdimms == *(p+10)) || (*(p+10 ) == 0xFE)) { - if((*p == Speed) || (*p == 0xFE)) { - if(MAAload <= *(p+1)) { + if ((*p == Speed) || (*p == 0xFE)) { + if (MAAload <= *(p+1)) { *AddrTmgCTL = stream_to_int((u8*)(p+2)); *ODC_CTL = stream_to_int((u8*)(p+6)); break; diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c index 8899c55b17..cac2342097 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk4.c +++ b/src/northbridge/amd/amdmct/mct/mctardk4.c @@ -33,7 +33,7 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, // print_tx("1 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]); // print_tx("1 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]); - if(pDCTstat->MAdimms[dct] == 1) + if (pDCTstat->MAdimms[dct] == 1) pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 75ohms */ else pDCTstat->CH_ODC_CTL[dct] |= 0x10000000; /* 150ohms */ @@ -107,9 +107,9 @@ static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, *CMDmode = 1; // FIXME: add Ax support - if(MAAdimms == 0) { + if (MAAdimms == 0) { *ODC_CTL = 0x00111222; - if(Speed == 3) + if (Speed == 3) *AddrTmgCTL = 0x00202220; else if (Speed == 2) *AddrTmgCTL = 0x002F2F00; @@ -121,21 +121,21 @@ static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, *AddrTmgCTL = 0x002F2020; else *AddrTmgCTL = 0x002F2F2F; - } else if(MAAdimms == 1) { - if(Speed == 4) { + } else if (MAAdimms == 1) { + if (Speed == 4) { *CMDmode = 2; *AddrTmgCTL = 0x00202520; *ODC_CTL = 0x00113222; - } else if(Speed == 5) { + } else if (Speed == 5) { *CMDmode = 2; *AddrTmgCTL = 0x002F2020; *ODC_CTL = 0x00113222; } else { *CMDmode = 1; *ODC_CTL = 0x00111222; - if(Speed == 3) { + if (Speed == 3) { *AddrTmgCTL = 0x00202220; - } else if(Speed == 2) { + } else if (Speed == 2) { if (MAAload == 4) *AddrTmgCTL = 0x002B2F00; else if (MAAload == 16) @@ -144,9 +144,9 @@ static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, *AddrTmgCTL = 0x002F2F00; else *AddrTmgCTL = 0x002F2F00; - } else if(Speed == 1) { + } else if (Speed == 1) { *AddrTmgCTL = 0x002F2F00; - } else if(Speed == 5) { + } else if (Speed == 5) { *AddrTmgCTL = 0x002F2020; } else { *AddrTmgCTL = 0x002F2F2F; @@ -156,8 +156,8 @@ static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, *CMDmode = 2; p = Table_ATC_ODC_D_Bx; do { - if(Speed == *p) { - if(MAAload <= *(p+1)) { + if (Speed == *p) { + if (MAAload <= *(p+1)) { *AddrTmgCTL = stream_to_int(p+2); *ODC_CTL = stream_to_int(p+6); break; diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c index 45b926b858..e8d26da45f 100644 --- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c @@ -64,7 +64,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, val = Get_NB32(dev, reg); val >>= (ChipSel>>1)<<2; val &= 0x0f; - if(EnChipSels == 1) + if (EnChipSels == 1) BankEncd = val; else /*If number of Rows/Columns not equal, skip */ @@ -79,13 +79,13 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, } if (DoIntlv) { - if(!_CsIntCap) { + if (!_CsIntCap) { pDCTstat->ErrStatus |= 1<<SB_BkIntDis; DoIntlv = 0; } } - if(DoIntlv) { + if (DoIntlv) { val = Tab_int_D[BankEncd]; if (pDCTstat->Status & (1<<SB_128bitmode)) val++; @@ -113,7 +113,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, val |= val_hi; Set_NB32(dev, reg, val); - if(ChipSel & 1) + if (ChipSel & 1) continue; reg = 0x60 + ((ChipSel>>1)<<2) + reg_off; /*Dram CS Mask 0 */ diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index abc5838c54..67ff823cb8 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -1118,7 +1118,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, /* New stuff */ val += ((1 << 21) >> 8); /* Add 2MB offset to avoid compat area */ if (val >= MCT_TRNG_KEEPOUT_START) { - while(val < MCT_TRNG_KEEPOUT_END) + while (val < MCT_TRNG_KEEPOUT_END) val += (1 << (15-8)); /* add 32K */ } diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index b2ac849b3d..5c1dc3a53c 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -121,12 +121,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(dev, reg); /* WE/RE is checked */ - if((val & 3)==3) { /* Node has dram populated */ + if ((val & 3)==3) { /* Node has dram populated */ /* Negate 'all nodes/dimms ECC' flag if non ecc memory populated */ - if( pDCTstat->Status & (1<<SB_ECCDIMMs)) { + if ( pDCTstat->Status & (1<<SB_ECCDIMMs)) { LDramECC = isDramECCEn_D(pDCTstat); - if(pDCTstat->ErrCode != SC_RunningOK) { + if (pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); @@ -137,7 +137,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } else { AllECC = 0; } - if(LDramECC) { /* if ECC is enabled on this dram */ + if (LDramECC) { /* if ECC is enabled on this dram */ if (OB_NBECC) { mct_EnableDatIntlv_D(pMCTstat, pDCTstat); dev = pDCTstat->dev_nbmisc; @@ -160,7 +160,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /* if Node present */ } - if(AllECC) + if (AllECC) pMCTstat->GStatus |= 1<<GSB_ECCDIMMs; else pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs); @@ -176,11 +176,11 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(pDCTstat->dev_map, reg); curBase = val & 0xffff0000; /*WE/RE is checked because memory config may have been */ - if((val & 3)==3) { /* Node has dram populated */ + if ((val & 3)==3) { /* Node has dram populated */ if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */ dev = pDCTstat->dev_nbmisc; val = curBase << 8; - if(OB_ECCRedir) { + if (OB_ECCRedir) { val |= (1<<0); /* enable redirection */ } Set_NB32(dev, 0x5C, val); /* Dram Scrub Addr Low */ @@ -205,7 +205,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /*if Node present */ } - if(mctGet_NVbits(NV_SyncOnUnEccEn)) + if (mctGet_NVbits(NV_SyncOnUnEccEn)) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); @@ -239,8 +239,8 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, reg = 0x40+(Node<<3); /* Dram Base Node 0 + index*/ val = Get_NB32(pDCTstat->dev_map, reg); /*WE/RE is checked because memory config may have been*/ - if((val & 3)==3) { /* Node has dram populated*/ - if( isDramECCEn_D(pDCTstat)) { + if ((val & 3)==3) { /* Node has dram populated*/ + if ( isDramECCEn_D(pDCTstat)) { /*if ECC is enabled on this dram*/ dev = pDCTstat->dev_nbmisc; reg = 0x44; /* MCA NB Configuration*/ @@ -274,7 +274,7 @@ static u32 GetScrubAddr_D(u32 Node) lo = Get_NB32(dev, regx); /* Scrub Addr High again, detect 32-bit wrap */ val = Get_NB32(dev, reg); - if(val != hi) { + if (val != hi) { hi = val; /* Scrub Addr Low again, if wrap occurred */ lo = Get_NB32(dev, regx); } @@ -295,16 +295,16 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) u8 ch_end; u8 isDimmECCEn = 0; - if(pDCTstat->GangedMode) { + if (pDCTstat->GangedMode) { ch_end = 1; } else { ch_end = 2; } - for(i=0; i<ch_end; i++) { - if(pDCTstat->DIMMValidDCT[i] > 0){ + for (i=0; i<ch_end; i++) { + if (pDCTstat->DIMMValidDCT[i] > 0){ reg = 0x90 + i * 0x100; /* Dram Config Low */ val = Get_NB32(dev, reg); - if(val & (1<<DimmEcEn)) { + if (val & (1<<DimmEcEn)) { /* set local flag 'dram ecc capable' */ isDimmECCEn = 1; break; diff --git a/src/northbridge/amd/amdmct/mct/mctgr.c b/src/northbridge/amd/amdmct/mct/mctgr.c index 01d729d701..a13d4e2f0f 100644 --- a/src/northbridge/amd/amdmct/mct/mctgr.c +++ b/src/northbridge/amd/amdmct/mct/mctgr.c @@ -31,13 +31,13 @@ u32 mct_AdjustMemClkDis_GR(struct DCTStatStruc *pDCTstat, u32 dct, DramTimingLo = val; /* Dram Timing Low (owns Clock Enable bits) */ NewDramTimingLo = Get_NB32(dev, 0x88 + reg_off); - if(mctGet_NVbits(NV_AllMemClks)==0) { + if (mctGet_NVbits(NV_AllMemClks)==0) { /*Special Jedec SPD diagnostic bit - "enable all clocks"*/ - if(!(pDCTstat->Status & (1<<SB_DiagClks))) { - for(i=0; i<MAX_DIMMS_SUPPORTED; i++) { + if (!(pDCTstat->Status & (1<<SB_DiagClks))) { + for (i=0; i<MAX_DIMMS_SUPPORTED; i++) { val = Tab_GRCLKDis[i]; - if(val<8) { - if(!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) { + if (val<8) { + if (!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) { /* disable memclk */ NewDramTimingLo |= (1<<(i+1)); } @@ -61,7 +61,7 @@ u32 mct_AdjustDramConfigLo_GR(struct DCTStatStruc *pDCTstat, u32 dct, u32 val) ; mov cx,PA_NBMISC+44h ;MCA NB Configuration ; call Get_NB32n_D ; bt eax,22 ;EccEn - ; .if(CARRY?) + ; .if (CARRY?) ; btr eax,BurstLength32 ; .endif */ @@ -72,7 +72,7 @@ u32 mct_AdjustDramConfigLo_GR(struct DCTStatStruc *pDCTstat, u32 dct, u32 val) void mct_AdjustMemHoist_GR(struct DCTStatStruc *pDCTstat, u32 base, u32 HoleSize) { u32 val; - if(base >= pDCTstat->DCTHoleBase) { + if (base >= pDCTstat->DCTHoleBase) { u32 dev = pDCTstat->dev_dct; base += HoleSize; base >>= 27 - 8; diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c index 06c642a865..5e91947e71 100644 --- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c @@ -44,15 +44,15 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, */ val = mctGet_NVbits(NV_BottomIO); - if(val == 0) + if (val == 0) val++; Bottom32bIO = val << (24-8); val = pMCTstat->SysLimit + 1; - if(val <= _4GB_RJ8) { + if (val <= _4GB_RJ8) { Bottom40bIO = 0; - if(Bottom32bIO >= val) + if (Bottom32bIO >= val) Bottom32bIO = val; } else { Bottom40bIO = val; @@ -90,7 +90,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, /* Base */ /* Limit */ /* MtrrAddr */ - if(addr == -1) /* ran out of MTRRs?*/ + if (addr == -1) /* ran out of MTRRs?*/ pMCTstat->GStatus |= 1<<GSB_MTRRshort; pMCTstat->Sub4GCacheTop = Cache32bTOP<<8; @@ -104,7 +104,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, _WRMSR(addr, lo, hi); print_tx("\t CPUMemTyping: Bottom32bIO:", Bottom32bIO); print_tx("\t CPUMemTyping: Bottom40bIO:", Bottom40bIO); - if(Bottom40bIO) { + if (Bottom40bIO) { hi = Bottom40bIO >> 24; lo = Bottom40bIO << 8; if (mctSetNodeBoundary_D()) @@ -114,7 +114,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, } addr = 0xC0010010; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); - if(Bottom40bIO) { + if (Bottom40bIO) { lo |= (1<<21); /* MtrrTom2En=1 */ lo |= (1<<22); /* Tom2ForceMemTypeWB */ } else { @@ -163,7 +163,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) val = curBase = Base; curLimit = *pLimit; addr = *pMtrrAddr; - while((addr >= 0x200) && (addr < 0x20C) && (val < *pLimit)) { + while ((addr >= 0x200) && (addr < 0x20C) && (val < *pLimit)) { /* start with "ascending" code path */ /* alignment (largest block size)*/ valx = 1 << bsf(curBase); @@ -171,7 +171,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) /* largest legal limit, given current non-zero range Base*/ valx += curBase; - if((curBase == 0) || (*pLimit < valx)) { + if ((curBase == 0) || (*pLimit < valx)) { /* flop direction to "descending" code path*/ valx = 1<<bsr(*pLimit - curBase); curSize = valx; @@ -194,7 +194,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) curBase = val; /* next Base = current Limit (loop exit)*/ addr++; /* next MTRR pair addr */ } - if(val < *pLimit) { + if (val < *pLimit) { *pLimit = val; addr = -1; } @@ -238,7 +238,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat addr = 0x200; lo = 0; hi = lo; - while( addr < 0x20C) { + while ( addr < 0x20C) { _WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */ addr++; /* next MTRR pair addr */ } @@ -248,7 +248,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat *======================================================================*/ print_tx("\t UMAMemTyping_D: Cache32bTOP:", Cache32bTOP); SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); - if(addr == -1) /* ran out of MTRRs?*/ + if (addr == -1) /* ran out of MTRRs?*/ pMCTstat->GStatus |= 1<<GSB_MTRRshort; } } diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c index 28c2751a56..32c319946b 100644 --- a/src/northbridge/amd/amdmct/mct/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c @@ -66,7 +66,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, _SWHole = 0; } - if(!_SWHole) { + if (!_SWHole) { Base = Get_NB32(dev0, reg0); if (Base & 1) { NodesWmem++; @@ -85,7 +85,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, * are the same on all nodes */ DctSelBase = Get_NB32(pDCTstat->dev_dct, 0x114); - if(DctSelBase) { + if (DctSelBase) { DctSelBase <<= 8; if ( pDCTstat->Status & (1 << SB_HWHole)) { if (DctSelBase >= 0x1000000) { @@ -150,7 +150,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, Base = ((Nodes - 1) << 8) | 3; reg0 = 0x40; Node = 0; - while(Node < Nodes) { + while (Node < Nodes) { Set_NB32(dev0, reg0, Base); MemSize = MemSize0; MemSize--; @@ -164,7 +164,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, /* set base/limit to F1x120/124 per Node */ Node = 0; - while(Node < Nodes) { + while (Node < Nodes) { pDCTstat = pDCTstatA + Node; pDCTstat->NodeSysBase = 0; MemSize = MemSize0; @@ -185,7 +185,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, HoleBase = pMCTstat->HoleBase; if (Dct0MemSize >= HoleBase) { val = HWHoleSz; - if( Node == 0) { + if ( Node == 0) { val += Dct0MemSize; } } else { diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index a6d6bad164..95afebf30e 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -24,7 +24,7 @@ u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val) tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { val &= 0x0FFFFFFF; - if(pDCTstat->MAdimms[dct] > 1) + if (pDCTstat->MAdimms[dct] > 1) val |= 0x10000000; } @@ -42,7 +42,7 @@ u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val) uint64_t tmp; tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - if(!(val & (3<<12) )) + if (!(val & (3<<12) )) val |= 1<<12; } return val; @@ -59,13 +59,13 @@ void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct) tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { - if(CheckNBCOFAutoPrechg(pDCTstat, dct)) { + if (CheckNBCOFAutoPrechg(pDCTstat, dct)) { dev = pDCTstat->dev_dct; reg_off = 0x100 * dct; reg = 0x90 + reg_off; /* Dram Configuration Lo */ val = Get_NB32(dev, reg); val |= 1<<ForceAutoPchg; - if(!pDCTstat->GangedMode) + if (!pDCTstat->GangedMode) val |= 1<<BurstLength32; Set_NB32(dev, reg, val); @@ -99,11 +99,11 @@ void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat, u32 val; u32 Node; - for(Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; - if(!pDCTstat->NodePresent) break; + if (!pDCTstat->NodePresent) break; tmp = pDCTstat->LogicalCPUID; if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { @@ -149,15 +149,15 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, dev = pDCTstat->dev_dct; index = 0; - for(Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel<2; Channel++) { index_reg = 0x98 + 0x100 * Channel; val = Get_NB32_index_wait(dev, index_reg, 0x0d004007); val |= 0x3ff; Set_NB32_index_wait(dev, index_reg, 0x0d0f4f07, val); } - for(Channel = 0; Channel<2; Channel++) { - if(pDCTstat->GangedMode && Channel) + for (Channel = 0; Channel<2; Channel++) { + if (pDCTstat->GangedMode && Channel) break; reg_off = 0x100 * Channel; reg = 0x78 + reg_off; @@ -167,11 +167,11 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, Set_NB32(dev, reg, val); } - for(Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel<2; Channel++) { reg_off = 0x100 * Channel; val = 0; index_reg = 0x98 + reg_off; - for( index = 0x30; index < (0x45 + 1); index++) { + for ( index = 0x30; index < (0x45 + 1); index++) { Set_NB32_index_wait(dev, index_reg, index, val); } } @@ -265,7 +265,7 @@ u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct) print_tx("NB COF:", valy >> NbDid); val = valy/valx; - if((val==3) && (valy%valx)) /* 3 < NClk/MemClk < 4 */ + if ((val==3) && (valy%valx)) /* 3 < NClk/MemClk < 4 */ ret = 1; return ret; @@ -286,8 +286,8 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { Speed = pDCTstat->Speed; /* MemClkFreq = 333MHz or 533MHz */ - if((Speed == 3) || (Speed == 2)) { - if(pDCTstat->GangedMode) { + if ((Speed == 3) || (Speed == 2)) { + if (pDCTstat->GangedMode) { ch_start = 0; ch_end = 2; } else { @@ -296,7 +296,7 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct) } dev = pDCTstat->dev_dct; index = 0x0D00E001; - for(ch=ch_start; ch<ch_end; ch++) { + for (ch=ch_start; ch<ch_end; ch++) { index_reg = 0x98 + 0x100 * ch; val = Get_NB32_index(dev, index_reg, 0x0D00E001); val &= ~(0xf0); @@ -332,7 +332,7 @@ static u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat, if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) { if (pDCTstat->Direction == DQS_WRITEDIR) { if ((pDCTstat->Speed == 2) || (pDCTstat->Speed == 3)) { - if(DQSDelay == 13) { + if (DQSDelay == 13) { if (*result == 0xFF) { for (ByteLane = 0; ByteLane < 8; ByteLane++) { pDCTstat->DQSDelay = 13; diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index 1881a37c54..510cf0dd4c 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -86,7 +86,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, p_A = (u32 *)SetupDqsPattern_1PassB(pass); p_B = (u32 *)SetupDqsPattern_1PassA(pass); - for(i=0;i<16;i++) { + for (i=0;i<16;i++) { buf_a[i] = p_A[i]; buf_b[i] = p_B[i]; } @@ -99,7 +99,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Pass) { - if(mct_checkNumberOfDqsRcvEn_1Pass(Pass)) + if (mct_checkNumberOfDqsRcvEn_1Pass(Pass)) dqsTrainRcvrEn_SW(pMCTstat, pDCTstat, Pass); } @@ -137,7 +137,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, dev = pDCTstat->dev_dct; ch_start = 0; - if(!pDCTstat->GangedMode) { + if (!pDCTstat->GangedMode) { ch_end = 2; } else { ch_end = 1; @@ -161,7 +161,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, print_t("TrainRcvrEn: 1\n"); cr4 = read_cr4(); - if(cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & ( 1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -171,7 +171,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, msr = HWCR; _RDMSR(msr, &lo, &hi); //FIXME: Why use SSEDIS - if(lo & (1 << 17)) { /* save the old value */ + if (lo & (1 << 17)) { /* save the old value */ _Wrap32Dis = 1; } lo |= (1 << 17); /* HWCR.wrap32dis */ @@ -182,15 +182,15 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); - if(pDCTstat->Speed == 1) { + if (pDCTstat->Speed == 1) { pDCTstat->T1000 = 5000; /* get the T1000 figure (cycle time (ns)*1K */ - } else if(pDCTstat->Speed == 2) { + } else if (pDCTstat->Speed == 2) { pDCTstat->T1000 = 3759; - } else if(pDCTstat->Speed == 3) { + } else if (pDCTstat->Speed == 3) { pDCTstat->T1000 = 3003; - } else if(pDCTstat->Speed == 4) { + } else if (pDCTstat->Speed == 4) { pDCTstat->T1000 = 2500; - } else if(pDCTstat->Speed == 5) { + } else if (pDCTstat->Speed == 5) { pDCTstat->T1000 = 1876; } else { pDCTstat->T1000 = 0; @@ -222,22 +222,22 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, print_debug_dqs("\t\tTrainRcvEnd52: index ", Addl_Index, 2); - if(!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) { + if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver)) { print_t("\t\t\tRank not enabled_D\n"); continue; } TestAddr0 = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, Channel, Receiver, &valid); - if(!valid) { /* Address not supported on current CS */ + if (!valid) { /* Address not supported on current CS */ print_t("\t\t\tAddress not supported on current CS\n"); continue; } TestAddr0B = TestAddr0 + (BigPagex8_RJ8 << 3); - if(mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver+1)) { + if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver+1)) { TestAddr1 = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, Channel, Receiver+1, &valid); - if(!valid) { /* Address not supported on current CS */ + if (!valid) { /* Address not supported on current CS */ print_t("\t\t\tAddress not supported on current CS+1\n"); continue; } @@ -266,11 +266,11 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, pDCTstat->DqsRcvEn_Saved = 0; - while(RcvrEnDly < RcvrEnDlyLimit) { /* sweep Delay value here */ + while (RcvrEnDly < RcvrEnDlyLimit) { /* sweep Delay value here */ print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3); /* callback not required - if(mct_AdjustDelay_D(pDCTstat, RcvrEnDly)) + if (mct_AdjustDelay_D(pDCTstat, RcvrEnDly)) goto skipDly; */ @@ -278,7 +278,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, and odd steps alternate. The pointers to the patterns will be swaped at the end of the loop so that they correspond. */ - if(RcvrEnDly & 1) { + if (RcvrEnDly & 1) { PatternA = 1; PatternB = 0; } else { @@ -289,7 +289,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0, PatternA); /* rank 0 of DIMM, testpattern 0 */ mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0B, PatternB); /* rank 0 of DIMM, testpattern 1 */ - if(_2Ranks) { + if (_2Ranks) { mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr1, PatternA); /*rank 1 of DIMM, testpattern 0 */ mct_Write1LTestPattern_D(pMCTstat, pDCTstat, TestAddr1B, PatternB); /*rank 1 of DIMM, testpattern 1 */ } @@ -309,7 +309,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, // != 0x00 mean pass - if(Test0 == DQS_PASS) { + if (Test0 == DQS_PASS) { mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0B); /*cache fills */ /* ROM vs cache compare */ Test1 = mct_CompareTestPatternQW0_D(pMCTstat, pDCTstat, TestAddr0B, Channel, PatternB, Pass); @@ -318,11 +318,11 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, print_debug_dqs("\t\t\tTrainRcvEn543: Test1 result ", Test1, 3); - if(Test1 == DQS_PASS) { + if (Test1 == DQS_PASS) { CurrTestSide0 = DQS_PASS; } } - if(_2Ranks) { + if (_2Ranks) { mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr1); /*cache fills */ /* ROM vs cache compare */ Test0 = mct_CompareTestPatternQW0_D(pMCTstat, pDCTstat, TestAddr1, Channel, PatternA, Pass); @@ -331,7 +331,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, print_debug_dqs("\t\t\tTrainRcvEn544: Test0 result ", Test0, 3); - if(Test0 == DQS_PASS) { + if (Test0 == DQS_PASS) { mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr1B); /*cache fills */ /* ROM vs cache compare */ Test1 = mct_CompareTestPatternQW0_D(pMCTstat, pDCTstat, TestAddr1B, Channel, PatternB, Pass); @@ -339,13 +339,13 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, ResetDCTWrPtr_D(dev, index_reg, Addl_Index); print_debug_dqs("\t\t\tTrainRcvEn545: Test1 result ", Test1, 3); - if(Test1 == DQS_PASS) { + if (Test1 == DQS_PASS) { CurrTestSide1 = DQS_PASS; } } } - if(_2Ranks) { + if (_2Ranks) { if ((CurrTestSide0 == DQS_PASS) && (CurrTestSide1 == DQS_PASS)) { CurrTest = DQS_PASS; } @@ -358,7 +358,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, valid = mct_SavePassRcvEnDly_D(pDCTstat, RcvrEnDly, Channel, Receiver, Pass); /* Break(1:RevF,2:DR) or not(0) FIXME: This comment deosn't make sense */ - if(valid == 2 || (LastTest == DQS_FAIL && valid == 1)) { + if (valid == 2 || (LastTest == DQS_FAIL && valid == 1)) { RcvrEnDlyRmin = RcvrEnDly; break; } @@ -384,14 +384,14 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDly ", RcvrEnDly, 2); print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDlyRmin ", RcvrEnDlyRmin, 3); print_debug_dqs("\t\tTrainRcvEn61: RcvrEnDlyLimit ", RcvrEnDlyLimit, 3); - if(RcvrEnDlyRmin == RcvrEnDlyLimit) { + if (RcvrEnDlyRmin == RcvrEnDlyLimit) { /* no passing window */ pDCTstat->ErrStatus |= 1 << SB_NORCVREN; Errors |= 1 << SB_NORCVREN; pDCTstat->ErrCode = SC_FatalErr; } - if(RcvrEnDly > (RcvrEnDlyLimit - 1)) { + if (RcvrEnDly > (RcvrEnDlyLimit - 1)) { /* passing window too narrow, too far delayed*/ pDCTstat->ErrStatus |= 1 << SB_SmallRCVR; Errors |= 1 << SB_SmallRCVR; @@ -406,12 +406,12 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, mct_SetFinalRcvrEnDly_D(pDCTstat, RcvrEnDly, Final_Value, Channel, Receiver, dev, index_reg, Addl_Index, Pass); - if(pDCTstat->ErrStatus & (1 << SB_SmallRCVR)) { + if (pDCTstat->ErrStatus & (1 << SB_SmallRCVR)) { Errors |= 1 << SB_SmallRCVR; } RcvrEnDly += Pass1MemClkDly; - if(RcvrEnDly > CTLRMaxDelay) { + if (RcvrEnDly > CTLRMaxDelay) { CTLRMaxDelay = RcvrEnDly; } @@ -430,7 +430,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, ResetDCTWrPtr_D(dev, index_reg, Addl_Index); - if(_DisableDramECC) { + if (_DisableDramECC) { mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } @@ -440,13 +440,13 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, mct_DisableDQSRcvEn_D(pDCTstat); } - if(!_Wrap32Dis) { + if (!_Wrap32Dis) { msr = HWCR; _RDMSR(msr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } - if(!_SSE2){ + if (!_SSE2){ cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -456,7 +456,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, { u8 Channel; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for(Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel<2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); } } @@ -470,9 +470,9 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, u8 *p; printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); - for(Channel = 0; Channel < 2; Channel++) { + for (Channel = 0; Channel < 2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x\n", Channel); - for(Receiver = 0; Receiver<8; Receiver+=2) { + for (Receiver = 0; Receiver<8; Receiver+=2) { printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver); p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1]; for (i=0;i<8; i++) { @@ -554,7 +554,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 *p; u32 val; - if(RcvrEnDly == 0xFE) { + if (RcvrEnDly == 0xFE) { /*set the boudary flag */ pDCTstat->Status |= 1 << SB_DQSRcvLimit; } @@ -562,8 +562,8 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, /* DimmOffset not needed for CH_D_B_RCVRDLY array */ - for(i=0; i < 8; i++) { - if(FinalValue) { + for (i=0; i < 8; i++) { + if (FinalValue) { /*calculate dimm offset */ p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; @@ -574,7 +574,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, index = Table_DQSRcvEn_Offset[i >> 1]; index += Addl_Index; /* DIMMx DqsRcvEn byte0 */ val = Get_NB32_index_wait(dev, index_reg, index); - if(i & 1) { + if (i & 1) { /* odd byte lane */ val &= ~(0xFF << 16); val |= (RcvrEnDly << 16); @@ -598,7 +598,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQ u32 val; u32 valx; - if(pDCTstat->GangedMode) + if (pDCTstat->GangedMode) Channel = 0; dev = pDCTstat->dev_dct; @@ -613,7 +613,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQ * add 1 MEMCLK to the sub-total. */ val = Get_NB32(dev, 0x90 + reg_off); - if(!(val & (1 << UnBuffDimm))) + if (!(val & (1 << UnBuffDimm))) SubTotal += 2; /* If the address prelaunch is setup for 1/2 MEMCLKs then @@ -621,7 +621,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQ * if (AddrCmdSetup || CsOdtSetup || CkeSetup) then K := K + 2; */ val = Get_NB32_index_wait(dev, index_reg, 0x04); - if(!(val & 0x00202020)) + if (!(val & 0x00202020)) SubTotal += 1; else SubTotal += 2; @@ -675,7 +675,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQ SubTotal += 5; pDCTstat->CH_MaxRdLat[Channel] = SubTotal; - if(pDCTstat->GangedMode) { + if (pDCTstat->GangedMode) { pDCTstat->CH_MaxRdLat[1] = SubTotal; } @@ -708,25 +708,25 @@ static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat, /* cmp if there has new DqsRcvEnDly to be recorded */ mask_Pass = pDCTstat->DqsRcvEn_Pass; - if(Pass == SecondPass) { + if (Pass == SecondPass) { mask_Pass = ~mask_Pass; } mask_Saved = pDCTstat->DqsRcvEn_Saved; - if(mask_Pass != mask_Saved) { + if (mask_Pass != mask_Saved) { /* find desired stack offset according to channel/dimm/byte */ - if(Pass == SecondPass) { + if (Pass == SecondPass) { // FIXME: SecondPass is never used for Barcelona p = pDCTstat->CH_D_B_RCVRDLY_1[Channel][receiver>>1]; p = 0; // Keep the compiler happy. } else { mask_Saved &= mask_Pass; p = pDCTstat->CH_D_B_RCVRDLY[Channel][receiver>>1]; } - for(i=0; i < 8; i++) { + for (i=0; i < 8; i++) { /* cmp per byte lane */ - if(mask_Pass & (1 << i)) { - if(!(mask_Saved & (1 << i))) { + if (mask_Pass & (1 << i)) { + if (!(mask_Saved & (1 << i))) { /* save RcvEnDly to stack, according to the related Dimm/byte lane */ p[i] = (u8)rcvrEnDly; @@ -756,8 +756,8 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, u8 value; - if(Pass == FirstPass) { - if(pattern==1) { + if (Pass == FirstPass) { + if (pattern==1) { test_buf = (u8 *)TestPattern1_D; } else { test_buf = (u8 *)TestPattern0_D; @@ -769,7 +769,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, SetUpperFSbase(addr); addr <<= 8; - if((pDCTstat->Status & (1<<SB_128bitmode)) && channel ) { + if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel ) { addr += 8; /* second channel */ test_buf += 8; } @@ -792,7 +792,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, /* if first pass, at least one byte lane pass * ,then DQS_PASS=1 and will set to related reg. */ - if(pDCTstat->DqsRcvEn_Pass != 0) { + if (pDCTstat->DqsRcvEn_Pass != 0) { result = DQS_PASS; } else { result = DQS_FAIL; @@ -802,7 +802,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, /* if second pass, at least one byte lane fail * ,then DQS_FAIL=1 and will set to related reg. */ - if(pDCTstat->DqsRcvEn_Pass != 0xFF) { + if (pDCTstat->DqsRcvEn_Pass != 0xFF) { result = DQS_FAIL; } else { result = DQS_PASS; @@ -812,7 +812,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, /* if second pass, we can't find the fail until FFh, * then let it fail to save the final delay */ - if((Pass == SecondPass) && (pDCTstat->Status & (1 << SB_DQSRcvLimit))) { + if ((Pass == SecondPass) && (pDCTstat->Status & (1 << SB_DQSRcvLimit))) { result = DQS_FAIL; pDCTstat->DqsRcvEn_Pass = 0; } @@ -820,7 +820,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat, /* second pass needs to be inverted * FIXME? this could be inverted in the above code to start with... */ - if(Pass == SecondPass) { + if (Pass == SecondPass) { if (result == DQS_PASS) { result = DQS_FAIL; } else if (result == DQS_FAIL) { /* FIXME: doesn't need to be else if */ @@ -843,7 +843,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, * Read Position is 1/2 Memclock Delay */ u8 i; - for(i=0;i<2; i++){ + for (i=0;i<2; i++){ InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -867,8 +867,8 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, // FIXME: add Cx support dword = 0x00000000; - for(i=1; i<=3; i++) { - for(j=0; j<dn; j++) + for (i=1; i<=3; i++) { + for (j=0; j<dn; j++) /* DIMM0 Write Data Timing Low */ /* DIMM0 Write ECC Timing */ Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword); @@ -876,14 +876,14 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, /* errata #180 */ dword = 0x2f2f2f2f; - for(i=5; i<=6; i++) { - for(j=0; j<dn; j++) + for (i=5; i<=6; i++) { + for (j=0; j<dn; j++) /* DIMM0 Read DQS Timing Control Low */ Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword); } dword = 0x0000002f; - for(j=0; j<dn; j++) + for (j=0; j<dn; j++) /* DIMM0 Read DQS ECC Timing Control */ Set_NB32_index_wait(dev, index_reg, 7 + 0x100 * j, dword); } @@ -903,7 +903,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) index = 0x12; p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); - for(ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { + for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; Set_NB32_index_wait(dev, index_reg, index, val); print_debug_dqs_pair("\t\tSetEccDQSRcvrPos: ChipSel ", @@ -925,7 +925,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, EccDQSScale = pDCTstat->CH_EccDQSScale[Channel]; for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { - if(mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { + if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u8 *p; p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; @@ -936,7 +936,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, * 2nd most like ECC byte lane */ val1 = p[(EccDQSLike>>8) & 0x07]; - if(val0 > val1) { + if (val0 > val1) { val = val0 - val1; } else { val = val1 - val0; @@ -945,7 +945,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, val *= ~EccDQSScale; val >>= 8; // /256 - if(val0 > val1) { + if (val0 > val1) { val -= val1; } else { val += val0; @@ -969,7 +969,7 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, if (!pDCTstat->NodePresent) break; if (pDCTstat->DCTSysLimit) { - for(i=0; i<2; i++) + for (i=0; i<2; i++) CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -987,7 +987,7 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, while (Node < MAX_NODES_SUPPORTED) { pDCTstat = pDCTstatA + Node; - if(pDCTstat->DCTSysLimit) { + if (pDCTstat->DCTSysLimit) { fenceDynTraining_D(pMCTstat, pDCTstat, 0); fenceDynTraining_D(pMCTstat, pDCTstat, 1); } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c index 9e069520aa..e059e1eff1 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c @@ -50,7 +50,7 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, MaxValue = 0; p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; - for(i=0; i < 8; i++) { + for (i=0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ val = p[i]; /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/ @@ -77,7 +77,7 @@ u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass) { u8 ret; ret = 0; - if((pDCTstat->DqsRcvEn_Pass == 0xff) && (pass== FirstPass)) + if ((pDCTstat->DqsRcvEn_Pass == 0xff) && (pass== FirstPass)) ret = 2; return ret; } diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c index daf2bdfe86..bd3c503097 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c @@ -24,7 +24,7 @@ u8 mct_checkNumberOfDqsRcvEn_Pass(u8 pass) u32 SetupDqsPattern_PassA(u8 Pass) { u32 ret; - if(Pass == FirstPass) + if (Pass == FirstPass) ret = (u32) TestPattern1_D; else ret = (u32) TestPattern2_D; @@ -36,7 +36,7 @@ u32 SetupDqsPattern_PassA(u8 Pass) u32 SetupDqsPattern_PassB(u8 Pass) { u32 ret; - if(Pass == FirstPass) + if (Pass == FirstPass) ret = (u32) TestPattern0_D; else ret = (u32) TestPattern2_D; @@ -66,12 +66,12 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, val = p[i]; // print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i); // print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val); - if(val > max) { + if (val > max) { max = val; } } RcvrEnDly = max; -// while(1) {; } +// while (1) {; } // RcvrEnDly += secPassOffset; //FIXME Why } @@ -100,7 +100,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, //FIXME: which byte? p_1 = pDCTstat->B_RCVRDLY_1; // p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; - for(i=0; i<bn; i++) { + for (i=0; i<bn; i++) { val = p[i]; /* left edge */ if (val != (RcvrEnDlyLimit - 1)) { @@ -120,7 +120,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } } else { - for(i=0; i < bn; i++) { + for (i=0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ //val += Pass1MemClkDly; diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c index ef37e3b419..0eb3c61b49 100644 --- a/src/northbridge/amd/amdmct/mct/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c @@ -79,7 +79,7 @@ static u32 SetupMaxRdPattern(struct MCTStatStruc *pMCTstat, buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); - for(i = 0; i < (16 * 3); i++) { + for (i = 0; i < (16 * 3); i++) { buf[i] = TestMaxRdLAtPattern_D[i]; } @@ -93,14 +93,14 @@ void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, { u8 Node; - for(Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; - if(!pDCTstat->NodePresent) + if (!pDCTstat->NodePresent) break; - if(pDCTstat->DCTSysLimit) + if (pDCTstat->DCTSysLimit) maxRdLatencyTrain_D(pMCTstat, pDCTstat); } } @@ -124,7 +124,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u32 pattern_buf; cr4 = read_cr4(); - if(cr4 & (1<<9)) { /* save the old value */ + if (cr4 & (1<<9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1<<9); /* OSFXSR enable SSE2 */ @@ -132,7 +132,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, addr = HWCR; _RDMSR(addr, &lo, &hi); - if(lo & (1<<17)) { /* save the old value */ + if (lo & (1<<17)) { /* save the old value */ _Wrap32Dis = 1; } lo |= (1<<17); /* HWCR.wrap32dis */ @@ -149,11 +149,11 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1); pDCTstat->Channel = Channel; - if( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel) + if ( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel) break; /*if ganged mode, skip DCT 1 */ TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid); - if(!valid) /* Address not supported on current CS */ + if (!valid) /* Address not supported on current CS */ continue; /* rank 1 of DIMM, testpattern 0 */ WriteMaxRdLat1CLTestPattern_D(pattern_buf, TestAddr0); @@ -161,10 +161,10 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, MaxRdLatDly = mct_GetStartMaxRdLat_D(pMCTstat, pDCTstat, Channel, RcvrEnDly, &Margin); print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly start ", MaxRdLatDly, 2); print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly Margin ", Margin, 2); - while(MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ + while (MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly); ReadMaxRdLat1CLTestPattern_D(TestAddr0); - if( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) + if ( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) break; SetTargetWTIO_D(TestAddr0); FlushMaxRdLatTestPattern_D(TestAddr0); @@ -175,17 +175,17 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly + Margin); } - if(_DisableDramECC) { + if (_DisableDramECC) { mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } - if(!_Wrap32Dis) { + if (!_Wrap32Dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if(!_SSE2){ + if (!_SSE2){ cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -195,7 +195,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, { u8 Channel; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); - for(Channel = 0; Channel<2; Channel++) { + for (Channel = 0; Channel<2; Channel++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]); } } @@ -253,7 +253,7 @@ static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr) print_debug_dqs_pair("\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value = ", val_test, 5); print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value = ", val, 5); - if(val != val_test) { + if (val != val_test) { ret = DQS_FAIL; break; } @@ -281,7 +281,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, bn = 8; - if(pDCTstat->Status & (1 << SB_128bitmode)) { + if (pDCTstat->Status & (1 << SB_128bitmode)) { ch_start = 0; ch_end = 2; } else { @@ -291,12 +291,12 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, *valid = 0; - for(ch = ch_start; ch < ch_end; ch++) { - for(d=0; d<4; d++) { - for(Byte = 0; Byte<bn; Byte++) { + for (ch = ch_start; ch < ch_end; ch++) { + for (d=0; d<4; d++) { + for (Byte = 0; Byte<bn; Byte++) { u8 tmp; tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; - if(tmp>Max) { + if (tmp>Max) { Max = tmp; Channel_Max = Channel; d_Max = d; @@ -305,11 +305,11 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, } } - if(mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1)) { + if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1)) { TestAddr0 = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1, valid); } - if(*valid) + if (*valid) *MaxRcvrEnDly = Max; return TestAddr0; @@ -328,7 +328,7 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, u32 reg_off; u32 dev; - if(pDCTstat->GangedMode) + if (pDCTstat->GangedMode) Channel = 0; index_reg = 0x98 + 0x100 * Channel; @@ -342,14 +342,14 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, /* If registered DIMMs are being used then add 1 MEMCLK to the sub-total*/ val = Get_NB32(dev, 0x90 + reg_off); - if(!(val & (1 << UnBuffDimm))) + if (!(val & (1 << UnBuffDimm))) SubTotal += 2; /*If the address prelaunch is setup for 1/2 MEMCLKs then add 1, * else add 2 to the sub-total. if (AddrCmdSetup || CsOdtSetup * || CkeSetup) then K := K + 2; */ val = Get_NB32_index_wait(dev, index_reg, 0x04); - if(!(val & 0x00202020)) + if (!(val & 0x00202020)) SubTotal += 1; else SubTotal += 2; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 7aee892b36..0c37366845 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -4313,7 +4313,7 @@ static void ClearDCT_D(struct MCTStatStruc *pMCTstat, reg_end = 0xA4; } - while(reg < reg_end) { + while (reg < reg_end) { if ((reg & 0xFF) == 0x84) { if (is_fam15h()) { val = Get_NB32_DCT(dev, dct, reg); @@ -5252,7 +5252,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, dword = 0; byte = 0xFF; - while(dword < MAX_CS_SUPPORTED) { + while (dword < MAX_CS_SUPPORTED) { if (pDCTstat->CSPresent & (1<<dword)){ /* re-enable clocks for the enabled CS */ val = p[dword]; @@ -8130,7 +8130,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, addr = HWCR; _RDMSR(addr, &lo, &hi); - if(lo & (1<<17)) { /* save the old value */ + if (lo & (1<<17)) { /* save the old value */ wrap32dis = 1; } lo |= (1<<17); /* HWCR.wrap32dis */ @@ -8158,7 +8158,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat, } } - if(!wrap32dis) { + if (!wrap32dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index 0d9c8863db..a7fac8f390 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -57,8 +57,8 @@ static u32 bsr(u32 x) u8 i; u32 ret = 0; - for(i=31; i>0; i--) { - if(x & (1<<i)) { + for (i=31; i>0; i--) { + if (x & (1<<i)) { ret = i; break; } @@ -73,8 +73,8 @@ static u32 bsf(u32 x) u8 i; u32 ret = 32; - for(i=0; i<32; i++) { - if(x & (1<<i)) { + for (i=0; i<32; i++) { + if (x & (1<<i)) { ret = i; break; } @@ -301,7 +301,7 @@ static u32 stream_to_int(u8 *p) val = 0; - for(i=3; i>=0; i--) { + for (i=3; i>=0; i--) { val <<= 8; valx = *(p+i); val |= valx; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c index f829f67ed0..3a14fd86b1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c @@ -65,12 +65,12 @@ static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, if (MAAdimms == 1) { *ODC_CTL = 0x00113222; *CMDmode = 1; - } else /* if(MAAdimms == 0) */ { - if(Speed == 4) { + } else /* if (MAAdimms == 0) */ { + if (Speed == 4) { *CMDmode = 1; - } else if(Speed == 5) { + } else if (Speed == 5) { *CMDmode = 1; - } else if(Speed == 6) { + } else if (Speed == 6) { *CMDmode = 2; } else { *CMDmode = 2; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c index 891f1d6710..3f013088ab 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c @@ -59,7 +59,7 @@ static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, *CMDmode = 1; if (mctGet_NVbits(NV_MAX_DIMMS) == 4) { - if(Speed == 4) { + if (Speed == 4) { *AddrTmgCTL = 0x00000000; } else if (Speed == 5) { *AddrTmgCTL = 0x003C3C3C; @@ -77,7 +77,7 @@ static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, *AddrTmgCTL = 0x00353935; } } else { - if(Speed == 4) { + if (Speed == 4) { *AddrTmgCTL = 0x00000000; if (MAAdimms == 3) *AddrTmgCTL = 0x00380038; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c index da7ce165ed..3f56765e4e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c @@ -62,7 +62,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, val = Get_NB32_DCT(dev, dct, reg); val >>= (ChipSel>>1)<<2; val &= 0x0f; - if(EnChipSels == 1) + if (EnChipSels == 1) BankEncd = val; else /*If number of Rows/Columns not equal, skip */ @@ -77,13 +77,13 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, } if (DoIntlv) { - if(!_CsIntCap) { + if (!_CsIntCap) { pDCTstat->ErrStatus |= 1<<SB_BkIntDis; DoIntlv = 0; } } - if(DoIntlv) { + if (DoIntlv) { val = Tab_int_D[BankEncd]; if (pDCTstat->Status & (1<<SB_128bitmode)) val++; @@ -111,7 +111,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, val |= val_hi; Set_NB32_DCT(dev, dct, reg, val); - if(ChipSel & 1) + if (ChipSel & 1) continue; reg = 0x60 + ((ChipSel>>1)<<2); /* Dram CS Mask 0 */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 8974a08e6e..06a70e6ebb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -476,7 +476,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, for (; Receiver < 8; Receiver++) { if ((Receiver & 0x1) == 0) { /* Even rank of DIMM */ - if(mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver+1)) + if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver+1)) dual_rank = 1; else dual_rank = 0; @@ -1296,7 +1296,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, dimm = (Receiver >> 1); if ((Receiver & 0x1) == 0) { /* Even rank of DIMM */ - if(mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, Receiver+1)) + if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, Receiver+1)) dual_rank = 1; else dual_rank = 0; @@ -2379,7 +2379,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat, /* New stuff */ val += ((1 << 21) >> 8); /* Add 2MB offset to avoid compat area */ if (val >= MCT_TRNG_KEEPOUT_START) { - while(val < MCT_TRNG_KEEPOUT_END) + while (val < MCT_TRNG_KEEPOUT_END) val += (1 << (15-8)); /* add 32K */ } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index c0ae440a64..5d31849fb4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -152,12 +152,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(dev, reg); /* WE/RE is checked */ - if((val & 3)==3) { /* Node has dram populated */ + if ((val & 3)==3) { /* Node has dram populated */ /* Negate 'all nodes/dimms ECC' flag if non ecc memory populated */ - if( pDCTstat->Status & (1<<SB_ECCDIMMs)) { + if ( pDCTstat->Status & (1<<SB_ECCDIMMs)) { LDramECC = isDramECCEn_D(pDCTstat); - if(pDCTstat->ErrCode != SC_RunningOK) { + if (pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); @@ -168,7 +168,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } else { AllECC = 0; } - if(LDramECC) { /* if ECC is enabled on this dram */ + if (LDramECC) { /* if ECC is enabled on this dram */ if (OB_NBECC) { mct_EnableDatIntlv_D(pMCTstat, pDCTstat); val = Get_NB32(pDCTstat->dev_dct, 0x110); @@ -194,7 +194,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /* if Node present */ } - if(AllECC) + if (AllECC) pMCTstat->GStatus |= 1<<GSB_ECCDIMMs; else pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs); @@ -210,7 +210,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) val = Get_NB32(pDCTstat->dev_map, reg); curBase = val & 0xffff0000; /*WE/RE is checked because memory config may have been */ - if((val & 3)==3) { /* Node has dram populated */ + if ((val & 3)==3) { /* Node has dram populated */ if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */ dev = pDCTstat->dev_nbmisc; val = curBase << 8; @@ -292,7 +292,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } - if(mctGet_NVbits(NV_SyncOnUnEccEn)) + if (mctGet_NVbits(NV_SyncOnUnEccEn)) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); @@ -325,8 +325,8 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat, reg = 0x40+(Node<<3); /* Dram Base Node 0 + index*/ val = Get_NB32(pDCTstat->dev_map, reg); /*WE/RE is checked because memory config may have been*/ - if((val & 3)==3) { /* Node has dram populated*/ - if( isDramECCEn_D(pDCTstat)) { + if ((val & 3)==3) { /* Node has dram populated*/ + if ( isDramECCEn_D(pDCTstat)) { /*if ECC is enabled on this dram*/ dev = pDCTstat->dev_nbmisc; reg = 0x44; /* MCA NB Configuration*/ @@ -348,16 +348,16 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat) u8 ch_end; u8 isDimmECCEn = 0; - if(pDCTstat->GangedMode) { + if (pDCTstat->GangedMode) { ch_end = 1; } else { ch_end = 2; } - for(i=0; i<ch_end; i++) { - if(pDCTstat->DIMMValidDCT[i] > 0){ + for (i=0; i<ch_end; i++) { + if (pDCTstat->DIMMValidDCT[i] > 0){ reg = 0x90; /* Dram Config Low */ val = Get_NB32_DCT(dev, i, reg); - if(val & (1<<DimmEcEn)) { + if (val & (1<<DimmEcEn)) { /* set local flag 'dram ecc capable' */ isDimmECCEn = 1; break; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c index b7c0476e57..8ed2befb34 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c @@ -43,15 +43,15 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, */ val = mctGet_NVbits(NV_BottomIO); - if(val == 0) + if (val == 0) val++; Bottom32bIO = val << (24-8); val = pMCTstat->SysLimit + 1; - if(val <= _4GB_RJ8) { + if (val <= _4GB_RJ8) { Bottom40bIO = 0; - if(Bottom32bIO >= val) + if (Bottom32bIO >= val) Bottom32bIO = val; } else { Bottom40bIO = val; @@ -89,7 +89,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, /* Base */ /* Limit */ /* MtrrAddr */ - if(addr == -1) /* ran out of MTRRs?*/ + if (addr == -1) /* ran out of MTRRs?*/ pMCTstat->GStatus |= 1<<GSB_MTRRshort; pMCTstat->Sub4GCacheTop = Cache32bTOP<<8; @@ -103,7 +103,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, _WRMSR(addr, lo, hi); printk(BIOS_DEBUG, "\t CPUMemTyping: Bottom32bIO:%x\n", Bottom32bIO); printk(BIOS_DEBUG, "\t CPUMemTyping: Bottom40bIO:%x\n", Bottom40bIO); - if(Bottom40bIO) { + if (Bottom40bIO) { hi = Bottom40bIO >> 24; lo = Bottom40bIO << 8; addr += 3; /* TOM2 */ @@ -111,7 +111,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, } addr = 0xC0010010; /* SYS_CFG */ _RDMSR(addr, &lo, &hi); - if(Bottom40bIO) { + if (Bottom40bIO) { lo |= (1<<21); /* MtrrTom2En=1 */ lo |= (1<<22); /* Tom2ForceMemTypeWB */ } else { @@ -158,7 +158,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) val = curBase = Base; curLimit = *pLimit; addr = *pMtrrAddr; - while((addr >= 0x200) && (addr < 0x20C) && (val < *pLimit)) { + while ((addr >= 0x200) && (addr < 0x20C) && (val < *pLimit)) { /* start with "ascending" code path */ /* alignment (largest block size)*/ valx = 1 << bsf(curBase); @@ -166,7 +166,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) /* largest legal limit, given current non-zero range Base*/ valx += curBase; - if((curBase == 0) || (*pLimit < valx)) { + if ((curBase == 0) || (*pLimit < valx)) { /* flop direction to "descending" code path*/ valx = 1<<bsr(*pLimit - curBase); curSize = valx; @@ -189,7 +189,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) curBase = val; /* next Base = current Limit (loop exit)*/ addr++; /* next MTRR pair addr */ } - if(val < *pLimit) { + if (val < *pLimit) { *pLimit = val; addr = -1; } @@ -234,7 +234,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat addr = 0x200; lo = 0; hi = lo; - while( addr < 0x20C) { + while ( addr < 0x20C) { _WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */ addr++; /* next MTRR pair addr */ } @@ -244,7 +244,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat *======================================================================*/ printk(BIOS_DEBUG, "\t UMAMemTyping_D: Cache32bTOP:%x\n", Cache32bTOP); SetMTRRrangeWB_D(0, &Cache32bTOP, &addr); - if(addr == -1) /* ran out of MTRRs?*/ + if (addr == -1) /* ran out of MTRRs?*/ pMCTstat->GStatus |= 1<<GSB_MTRRshort; } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c index f550bdde72..9a769adbaf 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c @@ -62,7 +62,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, _SWHole = 0; } - if(!_SWHole) { + if (!_SWHole) { Base = Get_NB32(dev0, reg0); if (Base & 1) { NodesWmem++; @@ -81,7 +81,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, * are the same on all nodes */ DctSelBase = Get_NB32(pDCTstat->dev_dct, 0x114); - if(DctSelBase) { + if (DctSelBase) { DctSelBase <<= 8; if ( pDCTstat->Status & (1 << SB_HWHole)) { if (DctSelBase >= 0x1000000) { @@ -145,7 +145,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, Base = ((Nodes - 1) << 8) | 3; reg0 = 0x40; Node = 0; - while(Node < Nodes) { + while (Node < Nodes) { Set_NB32(dev0, reg0, Base); MemSize = MemSize0; MemSize--; @@ -159,7 +159,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, /* set base/limit to F1x120/124 per Node */ Node = 0; - while(Node < Nodes) { + while (Node < Nodes) { pDCTstat = pDCTstatA + Node; pDCTstat->NodeSysBase = 0; MemSize = MemSize0; @@ -180,7 +180,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, HoleBase = pMCTstat->HoleBase; if (Dct0MemSize >= HoleBase) { val = HWHoleSz; - if( Node == 0) { + if ( Node == 0) { val += Dct0MemSize; } } else { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index f97b8c64d3..324e35e980 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -76,7 +76,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, p_A = (u32 *)SetupDqsPattern_1PassB(pass); p_B = (u32 *)SetupDqsPattern_1PassA(pass); - for(i=0;i<16;i++) { + for (i=0;i<16;i++) { buf_a[i] = p_A[i]; buf_b[i] = p_B[i]; } @@ -88,7 +88,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Pass) { - if(mct_checkNumberOfDqsRcvEn_1Pass(Pass)) { + if (mct_checkNumberOfDqsRcvEn_1Pass(Pass)) { if (is_fam15h()) dqsTrainRcvrEn_SW_Fam15(pMCTstat, pDCTstat, Pass); else @@ -560,7 +560,7 @@ static uint32_t convert_testaddr_and_channel_to_address(struct DCTStatStruc *pDC SetUpperFSbase(testaddr); testaddr <<= 8; - if((pDCTstat->Status & (1<<SB_128bitmode)) && channel ) { + if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel ) { testaddr += 8; /* second channel */ } @@ -614,7 +614,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, dev = pDCTstat->dev_dct; ch_start = 0; - if(!pDCTstat->GangedMode) { + if (!pDCTstat->GangedMode) { ch_end = 2; } else { ch_end = 1; @@ -636,7 +636,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, } cr4 = read_cr4(); - if(cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & ( 1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -644,7 +644,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, msr = rdmsr(HWCR); /* FIXME: Why use SSEDIS */ - if(msr.lo & (1 << 17)) { /* save the old value */ + if (msr.lo & (1 << 17)) { /* save the old value */ _Wrap32Dis = 1; } msr.lo |= (1 << 17); /* HWCR.wrap32dis */ @@ -729,9 +729,9 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, TestAddr0B = TestAddr0 + (BigPagex8_RJ8 << 3); - if(mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver+1)) { + if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, Receiver+1)) { TestAddr1 = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, Channel, Receiver+1, &valid); - if(!valid) { /* Address not supported on current CS */ + if (!valid) { /* Address not supported on current CS */ continue; } TestAddr1B = TestAddr1 + (BigPagex8_RJ8 << 3); @@ -972,7 +972,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, ResetDCTWrPtr_D(dev, Channel, index_reg, Addl_Index); } - if(_DisableDramECC) { + if (_DisableDramECC) { mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } @@ -981,12 +981,12 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, mct_DisableDQSRcvEn_D(pDCTstat); } - if(!_Wrap32Dis) { + if (!_Wrap32Dis) { msr = rdmsr(HWCR); msr.lo &= ~(1<<17); /* restore HWCR.wrap32dis */ wrmsr(HWCR, msr); } - if(!_SSE2){ + if (!_SSE2){ cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -996,7 +996,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1011,9 +1011,9 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, u16 *p; printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); - for(ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); - for(ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) { + for (ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i=0;i<8; i++) { @@ -1246,7 +1246,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, } cr4 = read_cr4(); - if(cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & ( 1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -1255,7 +1255,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, msr = HWCR; _RDMSR(msr, &lo, &hi); /* FIXME: Why use SSEDIS */ - if(lo & (1 << 17)) { /* save the old value */ + if (lo & (1 << 17)) { /* save the old value */ _Wrap32Dis = 1; } lo |= (1 << 17); /* HWCR.wrap32dis */ @@ -1485,7 +1485,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Calculate and program MaxRdLatency */ Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, Channel, 0); - if(_DisableDramECC) { + if (_DisableDramECC) { mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } @@ -1494,13 +1494,13 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, mct_DisableDQSRcvEn_D(pDCTstat); } - if(!_Wrap32Dis) { + if (!_Wrap32Dis) { msr = HWCR; _RDMSR(msr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } - if(!_SSE2){ + if (!_SSE2){ cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -1510,7 +1510,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); - for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1525,9 +1525,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, u16 *p; printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n"); - for(ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD); - for(ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) { + for (ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) { printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD); p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1]; for (i=0;i<8; i++) { @@ -1604,7 +1604,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, ch_end = 2; cr4 = read_cr4(); - if(cr4 & ( 1 << 9)) { /* save the old value */ + if (cr4 & ( 1 << 9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1 << 9); /* OSFXSR enable SSE2 */ @@ -1613,7 +1613,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, msr = HWCR; _RDMSR(msr, &lo, &hi); /* FIXME: Why use SSEDIS */ - if(lo & (1 << 17)) { /* save the old value */ + if (lo & (1 << 17)) { /* save the old value */ _Wrap32Dis = 1; } lo |= (1 << 17); /* HWCR.wrap32dis */ @@ -1710,17 +1710,17 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); } - if(_DisableDramECC) { + if (_DisableDramECC) { mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } - if(!_Wrap32Dis) { + if (!_Wrap32Dis) { msr = HWCR; _RDMSR(msr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(msr, lo, hi); } - if(!_SSE2){ + if (!_SSE2){ cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -1730,7 +1730,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "TrainMaxRdLatency: CH_MaxRdLat:\n"); - for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } @@ -1794,14 +1794,14 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, u16 *p; u32 val; - if(RcvrEnDly == 0x1fe) { + if (RcvrEnDly == 0x1fe) { /*set the boundary flag */ pDCTstat->Status |= 1 << SB_DQSRcvLimit; } /* DimmOffset not needed for CH_D_B_RCVRDLY array */ - for(i=0; i < 8; i++) { - if(FinalValue) { + for (i=0; i < 8; i++) { + if (FinalValue) { /*calculate dimm offset */ p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; RcvrEnDly = p[i]; @@ -1812,7 +1812,7 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly, index = Table_DQSRcvEn_Offset[i >> 1]; index += Addl_Index; /* DIMMx DqsRcvEn byte0 */ val = Get_NB32_index_wait_DCT(dev, Channel, index_reg, index); - if(i & 1) { + if (i & 1) { /* odd byte lane */ val &= ~(0x1ff << 16); val |= ((RcvrEnDly & 0x1ff) << 16); @@ -1865,7 +1865,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D cpu_val_p = 11; } - if(pDCTstat->GangedMode) + if (pDCTstat->GangedMode) Channel = 0; dev = pDCTstat->dev_dct; @@ -1879,7 +1879,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D * add 1 MEMCLK to the sub-total. */ val = Get_NB32_DCT(dev, Channel, 0x90); - if(!(val & (1 << UnBuffDimm))) + if (!(val & (1 << UnBuffDimm))) SubTotal += 2; /* If the address prelaunch is setup for 1/2 MEMCLKs then @@ -1887,7 +1887,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D * if (AddrCmdSetup || CsOdtSetup || CkeSetup) then K := K + 2; */ val = Get_NB32_index_wait_DCT(dev, Channel, index_reg, 0x04); - if(!(val & 0x00202020)) + if (!(val & 0x00202020)) SubTotal += 1; else SubTotal += 2; @@ -1925,7 +1925,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D SubTotal += (cpu_val_n) / 2; pDCTstat->CH_MaxRdLat[Channel][0] = SubTotal; - if(pDCTstat->GangedMode) { + if (pDCTstat->GangedMode) { pDCTstat->CH_MaxRdLat[1][0] = SubTotal; } @@ -1950,7 +1950,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, * Read Position is 1/2 Memclock Delay */ u8 i; - for(i=0;i<2; i++){ + for (i=0;i<2; i++){ InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i); } } @@ -1972,8 +1972,8 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, /* FIXME: add Cx support */ dword = 0x00000000; - for(i=1; i<=3; i++) { - for(j=0; j<dn; j++) + for (i=1; i<=3; i++) { + for (j=0; j<dn; j++) /* DIMM0 Write Data Timing Low */ /* DIMM0 Write ECC Timing */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword); @@ -1981,14 +1981,14 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, /* errata #180 */ dword = 0x2f2f2f2f; - for(i=5; i<=6; i++) { - for(j=0; j<dn; j++) + for (i=5; i<=6; i++) { + for (j=0; j<dn; j++) /* DIMM0 Read DQS Timing Control Low */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword); } dword = 0x0000002f; - for(j=0; j<dn; j++) + for (j=0; j<dn; j++) /* DIMM0 Read DQS ECC Timing Control */ Set_NB32_index_wait_DCT(dev, Channel, index_reg, 7 + 0x100 * j, dword); } @@ -2007,7 +2007,7 @@ void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel) index = 0x12; p = pDCTstat->CH_D_BC_RCVRDLY[Channel]; print_debug_dqs("\t\tSetEccDQSRcvrPos: Channel ", Channel, 2); - for(ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { + for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { val = p[ChipSel>>1]; Set_NB32_index_wait_DCT(dev, Channel, index_reg, index, val); print_debug_dqs_pair("\t\tSetEccDQSRcvrPos: ChipSel ", @@ -2029,7 +2029,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, EccDQSScale = pDCTstat->CH_EccDQSScale[Channel]; for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel += 2) { - if(mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { + if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel, ChipSel)) { u16 *p; p = pDCTstat->CH_D_B_RCVRDLY[Channel][ChipSel>>1]; @@ -2049,7 +2049,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, * 2nd most like ECC byte lane */ val1 = p[(EccDQSLike>>8) & 0x07]; - if(val0 > val1) { + if (val0 > val1) { val = val0 - val1; } else { val = val1 - val0; @@ -2058,7 +2058,7 @@ static void CalcEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, val *= ~EccDQSScale; val >>= 8; /* /256 */ - if(val0 > val1) { + if (val0 > val1) { val -= val1; } else { val += val0; @@ -2087,7 +2087,7 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, if (!pDCTstat->NodePresent) break; if (pDCTstat->DCTSysLimit) { - for(i=0; i<2; i++) + for (i=0; i<2; i++) CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i); } } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c index 15e66c934c..d5357355cd 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c @@ -49,7 +49,7 @@ static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel MaxValue = 0; p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1]; - for(i=0; i < 8; i++) { + for (i=0; i < 8; i++) { /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/ val = p[i]; /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/ @@ -69,7 +69,7 @@ u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass) { u8 ret; ret = 0; - if((pDCTstat->DqsRcvEn_Pass == 0xff) && (pass== FirstPass)) + if ((pDCTstat->DqsRcvEn_Pass == 0xff) && (pass== FirstPass)) ret = 2; return ret; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c index c386fce087..2f4d4da82b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c @@ -23,7 +23,7 @@ u8 mct_checkNumberOfDqsRcvEn_Pass(u8 pass) u32 SetupDqsPattern_PassA(u8 Pass) { u32 ret; - if(Pass == FirstPass) + if (Pass == FirstPass) ret = (u32) TestPattern1_D; else ret = (u32) TestPattern2_D; @@ -34,7 +34,7 @@ u32 SetupDqsPattern_PassA(u8 Pass) u32 SetupDqsPattern_PassB(u8 Pass) { u32 ret; - if(Pass == FirstPass) + if (Pass == FirstPass) ret = (u32) TestPattern0_D; else ret = (u32) TestPattern2_D; @@ -61,7 +61,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, for ( i=0;i<bn; i++) { val = p[i]; - if(val > max) { + if (val > max) { max = val; } } @@ -91,7 +91,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, /* FIXME: which byte? */ p_1 = pDCTstat->B_RCVRDLY_1; /* p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ - for(i=0; i<bn; i++) { + for (i=0; i<bn; i++) { val = p[i]; /* left edge */ if (val != (RcvrEnDlyLimit - 1)) { @@ -111,7 +111,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } } else { - for(i=0; i < bn; i++) { + for (i=0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ /* val += Pass1MemClkDly; */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 8cda2f8db0..15eb67e15b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -77,7 +77,7 @@ static u32 SetupMaxRdPattern(struct MCTStatStruc *pMCTstat, buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0)); - for(i = 0; i < (16 * 3); i++) { + for (i = 0; i < (16 * 3); i++) { buf[i] = TestMaxRdLAtPattern_D[i]; } @@ -89,14 +89,14 @@ void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, { u8 Node; - for(Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; - if(!pDCTstat->NodePresent) + if (!pDCTstat->NodePresent) break; - if(pDCTstat->DCTSysLimit) + if (pDCTstat->DCTSysLimit) maxRdLatencyTrain_D(pMCTstat, pDCTstat); } } @@ -119,7 +119,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u32 pattern_buf; cr4 = read_cr4(); - if(cr4 & (1<<9)) { /* save the old value */ + if (cr4 & (1<<9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1<<9); /* OSFXSR enable SSE2 */ @@ -127,7 +127,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, addr = HWCR; _RDMSR(addr, &lo, &hi); - if(lo & (1<<17)) { /* save the old value */ + if (lo & (1<<17)) { /* save the old value */ _Wrap32Dis = 1; } lo |= (1<<17); /* HWCR.wrap32dis */ @@ -144,11 +144,11 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1); pDCTstat->Channel = Channel; - if( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel) + if ( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel) break; /*if ganged mode, skip DCT 1 */ TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid); - if(!valid) /* Address not supported on current CS */ + if (!valid) /* Address not supported on current CS */ continue; /* rank 1 of DIMM, testpattern 0 */ WriteMaxRdLat1CLTestPattern_D(pattern_buf, TestAddr0); @@ -156,10 +156,10 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, MaxRdLatDly = mct_GetStartMaxRdLat_D(pMCTstat, pDCTstat, Channel, RcvrEnDly, &Margin); print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly start ", MaxRdLatDly, 2); print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly Margin ", Margin, 2); - while(MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ + while (MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly); ReadMaxRdLat1CLTestPattern_D(TestAddr0); - if( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) + if ( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) break; SetTargetWTIO_D(TestAddr0); FlushMaxRdLatTestPattern_D(TestAddr0); @@ -170,17 +170,17 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly + Margin); } - if(_DisableDramECC) { + if (_DisableDramECC) { mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } - if(!_Wrap32Dis) { + if (!_Wrap32Dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } - if(!_SSE2){ + if (!_SSE2){ cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); @@ -190,7 +190,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, { u8 ChannelDTD; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); - for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { + for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } @@ -245,7 +245,7 @@ static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr) print_debug_dqs_pair("\t\t\t\t\t\ttest_buf = ", (u32)test_buf, " value = ", val_test, 5); print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ", addr_lo, " value = ", val, 5); - if(val != val_test) { + if (val != val_test) { ret = DQS_FAIL; break; } @@ -273,7 +273,7 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, bn = 8; - if(pDCTstat->Status & (1 << SB_128bitmode)) { + if (pDCTstat->Status & (1 << SB_128bitmode)) { ch_start = 0; ch_end = 2; } else { @@ -283,12 +283,12 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, *valid = 0; - for(ch = ch_start; ch < ch_end; ch++) { - for(d=0; d<4; d++) { - for(Byte = 0; Byte<bn; Byte++) { + for (ch = ch_start; ch < ch_end; ch++) { + for (d=0; d<4; d++) { + for (Byte = 0; Byte<bn; Byte++) { u8 tmp; tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte]; - if(tmp>Max) { + if (tmp>Max) { Max = tmp; Channel_Max = Channel; d_Max = d; @@ -297,11 +297,11 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat, } } - if(mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1)) { + if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1)) { TestAddr0 = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, Channel_Max, d_Max << 1, valid); } - if(*valid) + if (*valid) *MaxRcvrEnDly = Max; return TestAddr0; @@ -318,7 +318,7 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 dev; - if(pDCTstat->GangedMode) + if (pDCTstat->GangedMode) Channel = 0; index_reg = 0x98; @@ -331,14 +331,14 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat, /* If registered DIMMs are being used then add 1 MEMCLK to the sub-total*/ val = Get_NB32_DCT(dev, Channel, 0x90); - if(!(val & (1 << UnBuffDimm))) + if (!(val & (1 << UnBuffDimm))) SubTotal += 2; /*If the address prelaunch is setup for 1/2 MEMCLKs then add 1, * else add 2 to the sub-total. if (AddrCmdSetup || CsOdtSetup * || CkeSetup) then K := K + 2; */ val = Get_NB32_index_wait_DCT(dev, Channel, index_reg, 0x04); - if(!(val & 0x00202020)) + if (!(val & 0x00202020)) SubTotal += 1; else SubTotal += 2; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index ffc6fb2df0..5c30bc554c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -1382,12 +1382,12 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 * - Program seed gross delay as 2 (gross is 4 or 6) or 1 (gross is 5). * - Keep original seed gross delay for later reference. */ - if(grossDelayValue >= 3) + if (grossDelayValue >= 3) grossDelayValue = (grossDelayValue&1)? 1 : 2; fineDelayValue = pDCTData->WLFineDelay[index+ByteLane]; if (ByteLane < 4) ValueLow |= ((grossDelayValue << 5) | fineDelayValue) << 8*ByteLane; - else if(ByteLane < 8) + else if (ByteLane < 8) ValueHigh |= ((grossDelayValue << 5) | fineDelayValue) << 8*(ByteLane-4); else EccValue = ((grossDelayValue << 5) | fineDelayValue); @@ -1505,7 +1505,7 @@ void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 if (pDCTData->WLGrossDelay[index+ByteLane] >= 3) { gross += pDCTData->WLGrossDelay[index+ByteLane]; - if(pDCTData->WLGrossDelay[index+ByteLane] & 1) + if (pDCTData->WLGrossDelay[index+ByteLane] & 1) gross -= 1; else gross -= 2; diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 12115c5aaf..0ba2d33a7f 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -492,7 +492,7 @@ static void vErratum372(struct DCTStatStruc *pDCTstat) static void vErratum414(struct DCTStatStruc *pDCTstat) { int dct=0; - for(; dct < 2 ; dct++) + for (; dct < 2 ; dct++) { int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); int powerDown = dRAMConfigHi & (1 << PowerDownEn ); |