diff options
| author | Timothy Pearson <tpearson@raptorengineering.com> | 2017-01-09 17:54:35 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-11 17:11:58 +0100 |
| commit | 590a3e1f6ccce873bb8f2129dc3680cab12e5a42 (patch) | |
| tree | 38866c351dff167e404afc33dd64ec18a25e69fe /src/northbridge/amd/amdmct | |
| parent | 7d484106319a0f4261eb17326dd9fe31e2d4e401 (diff) | |
amd/mct/ddr3: Avoid using uninitialized register address in ECC setup
Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as
a register address under certain conditions. Refactor mct_EnableDimmEccEn_D
to use the explicit address of the register in all cases.
Found-by: Coverity Scan #1347337
Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18079
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/amd/amdmct')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 9783f38993..10d4206559 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -2242,23 +2242,20 @@ void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC) { u32 val; - u32 reg; u32 dev; /* Enable ECC correction if it was previously disabled */ - dev = pDCTstat->dev_dct; if ((_DisableDramECC & 0x01) == 0x01) { - reg = 0x90; - val = Get_NB32_DCT(dev, 0, reg); + val = Get_NB32_DCT(dev, 0, 0x90); val |= (1<<DimmEcEn); - Set_NB32_DCT(dev, 0, reg, val); + Set_NB32_DCT(dev, 0, 0x90, val); } if ((_DisableDramECC & 0x02) == 0x02) { - val = Get_NB32_DCT(dev, 1, reg); + val = Get_NB32_DCT(dev, 1, 0x90); val |= (1<<DimmEcEn); - Set_NB32_DCT(dev, 1, reg, val); + Set_NB32_DCT(dev, 1, 0x90, val); } } |