Uniformly spell frequency unit symbol as Hz

Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6384
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

9 files changed, 104 insertions, 104 deletions

diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h
index a8f7d70ca8..da0d01b093 100644
--- a/src/northbridge/amd/amdmct/mct/mct.h
+++ b/src/northbridge/amd/amdmct/mct/mct.h
@@ -28,8 +28,8 @@
 
 #define J_MIN		0		/* j loop constraint. 1=CL 2.0 T*/
 #define J_MAX		4		/* j loop constraint. 4=CL 6.0 T*/
-#define K_MIN		1		/* k loop constraint. 1=200 Mhz*/
-#define K_MAX		4		/* k loop constraint. 9=400 Mhz*/
+#define K_MIN		1		/* k loop constraint. 1=200 MHz*/
+#define K_MAX		4		/* k loop constraint. 9=400 MHz*/
 #define CL_DEF		2		/* Default value for failsafe operation. 2=CL 4.0 T*/
 #define T_DEF		1		/* Default value for failsafe operation. 1=5ns (cycle time)*/
 
@@ -236,10 +236,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u8 DATAload[2];		/* Number of ranks loading CH A DATA*/
 					/* Number of ranks loading CH B DATA*/
 	u8 DIMMAutoSpeed;		/* Max valid Mfg. Speed of DIMMs
-					   1=200Mhz
-					   2=266Mhz
-					   3=333Mhz
-					   4=400Mhz */
+					   1=200MHz
+					   2=266MHz
+					   3=333MHz
+					   4=400MHz */
 	u8 DIMMCASL;		/* Min valid Mfg. CL bitfield
 					   0=2.0
 					   1=3.0
@@ -255,10 +255,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u16 DIMMTrrd;	/* Minimax Trrd*40 (ns) of DIMMs*/
 	u16 DIMMTwtr;	/* Minimax Twtr*40 (ns) of DIMMs*/
 	u8 Speed;		/* Bus Speed (to set Controller)
-				   1=200Mhz
-				   2=266Mhz
-				   3=333Mhz
-				   4=400Mhz */
+				   1=200MHz
+				   2=266MHz
+				   3=333MHz
+				   4=400MHz */
 	u8 CASL;		/* CAS latency DCT setting
 				   0=2.0
 				   1=3.0
@@ -288,10 +288,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u32 DCTHoleBase;	/* If not zero, BASE[39:8] (system address) of dram hole for HW remapping.  Dram hole exists on this Node's DCTs. */
 	u32 DCTSysLimit;	/* LIMIT[39:8] (system address) of this Node's DCTs */
 	u16 PresetmaxFreq;	/* Maximum OEM defined DDR frequency
-				   200=200Mhz (DDR400)
-				   266=266Mhz (DDR533)
-				   333=333Mhz (DDR667)
-				   400=400Mhz (DDR800) */
+				   200=200MHz (DDR400)
+				   266=266MHz (DDR533)
+				   333=333MHz (DDR667)
+				   400=400MHz (DDR800) */
 	u8 _2Tmode;	/* 1T or 2T CMD mode (slow access mode)
 				   1=1T
 				   2=2T */
@@ -408,10 +408,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 #define NV_MAX_NODES		1	/* Number of Nodes/Sockets (4-bits)*/
 #define NV_MAX_DIMMS		2	/* Number of DIMM slots for the specified Node ID (4-bits)*/
 #define NV_MAX_MEMCLK		3	/* Maximum platform demonstrated Memclock (10-bits)
-					   200=200Mhz (DDR400)
-					   266=266Mhz (DDR533)
-					   333=333Mhz (DDR667)
-					   400=400Mhz (DDR800)*/
+					   200=200MHz (DDR400)
+					   266=266MHz (DDR533)
+					   333=333MHz (DDR667)
+					   400=400MHz (DDR800)*/
 #define NV_ECC_CAP		4	/* Bus ECC capable (1-bits)
 					   0=Platform not capable
 					   1=Platform is capable*/
@@ -433,10 +433,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 					   1=Auto, user limit provided in NV_MemCkVal
 					   2=Manual, user value provided in NV_MemCkVal*/
 #define NV_MemCkVal		11	/* Memory Clock Value (2-bits)
-					   0=200Mhz
-					   1=266Mhz
-					   2=333Mhz
-					   3=400Mhz*/
+					   0=200MHz
+					   1=266MHz
+					   2=333MHz
+					   3=400MHz*/
 
 /* Dram Configuration */
 #define NV_BankIntlv		20	/* Dram Bank (chip-select) Interleaving (1-bits)
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 66eb88a7e9..924c5fb645 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -203,7 +203,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
 	 *     entry
 	 * 6. All var MTRRs reset to zero
 	 * 7. State of NB_CFG.DisDatMsk set properly on all CPUs
-	 * 8. All CPUs at 2Ghz Speed (unless DQS training is not installed).
+	 * 8. All CPUs at 2GHz Speed (unless DQS training is not installed).
 	 * 9. All cHT links at max Speed/Width (unless DQS training is not
 	 *     installed).
 	 *
@@ -212,11 +212,11 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
 	 * j CL(j)       k   F(k)
 	 * --------------------------
 	 * 0 2.0         -   -
-	 * 1 3.0         1   200 Mhz
-	 * 2 4.0         2   266 Mhz
-	 * 3 5.0         3   333 Mhz
-	 * 4 6.0         4   400 Mhz
-	 * 5 7.0         5   533 Mhz
+	 * 1 3.0         1   200 MHz
+	 * 2 4.0         2   266 MHz
+	 * 3 5.0         3   333 MHz
+	 * 4 6.0         4   400 MHz
+	 * 5 7.0         5   533 MHz
 	 */
 	u8 Node, NodesWmem;
 	u32 node_sys_base;
@@ -437,9 +437,9 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 				 * when 400, 533, 667, it will support dimm0/1/2/3,
 				 * and set conf for dimm0, hw will copy to dimm1/2/3
 				 * set for dimm1, hw will copy to dimm3
-				 * Rev A/B only support DIMM0/1 when 800Mhz and above
+				 * Rev A/B only support DIMM0/1 when 800MHz and above
 				 *   + 0x100 to next dimm
-				 * Rev C support DIMM0/1/2/3 when 800Mhz and above
+				 * Rev C support DIMM0/1/2/3 when 800MHz and above
 				 *   + 0x100 to next dimm
 				*/
 				for (DIMM = 0; DIMM < 2; DIMM++) {
@@ -3615,7 +3615,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
 	u32 dev = pDCTstat->dev_dct;
 
 	// FIXME: skip for Ax
-	if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533Mhz
+	if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
 		for (i=0; i < 2; i++) {
 			reg_off = 0x100 * i;
 			Set_NB32(dev,  0x98 + reg_off, 0x0D000030);
@@ -3630,7 +3630,7 @@ static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat,
 			struct DCTStatStruc *pDCTstat, u8 *dqs_pos)
 {
 	// FIXME: Skip for Ax
-	if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533Mhz
+	if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
 		*dqs_pos = 32;
 	}
 }
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
index 4370b8da96..0a1f925291 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d.h
@@ -35,8 +35,8 @@
 
 #define J_MIN		0		/* j loop constraint. 1=CL 2.0 T*/
 #define J_MAX		5		/* j loop constraint. 5=CL 7.0 T*/
-#define K_MIN		1		/* k loop constraint. 1=200 Mhz*/
-#define K_MAX		5		/* k loop constraint. 5=533 Mhz*/
+#define K_MIN		1		/* k loop constraint. 1=200 MHz*/
+#define K_MAX		5		/* k loop constraint. 5=533 MHz*/
 #define CL_DEF		2		/* Default value for failsafe operation. 2=CL 4.0 T*/
 #define T_DEF		1		/* Default value for failsafe operation. 1=5ns (cycle time)*/
 
@@ -325,11 +325,11 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u8 DATAload[2];		/*Number of ranks loading CH A DATA*/
 		/* Number of ranks loading CH B DATA*/
 	u8 DIMMAutoSpeed;	/*Max valid Mfg. Speed of DIMMs
-		1=200Mhz
-		2=266Mhz
-		3=333Mhz
-		4=400Mhz
-		5=533Mhz*/
+		1=200MHz
+		2=266MHz
+		3=333MHz
+		4=400MHz
+		5=533MHz*/
 	u8 DIMMCASL;		/* Min valid Mfg. CL bitfield
 		0=2.0
 		1=3.0
@@ -345,10 +345,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u16 DIMMTrrd;		/* Minimax Trrd*40 (ns) of DIMMs*/
 	u16 DIMMTwtr;		/* Minimax Twtr*40 (ns) of DIMMs*/
 	u8 Speed;		/* Bus Speed (to set Controller)
-		1=200Mhz
-		2=266Mhz
-		3=333Mhz
-		4=400Mhz */
+		1=200MHz
+		2=266MHz
+		3=333MHz
+		4=400MHz */
 	u8 CASL;		/* CAS latency DCT setting
 		0=2.0
 		1=3.0
@@ -378,10 +378,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u32 DCTHoleBase;	/* If not zero, BASE[39:8] (system address) of dram hole for HW remapping.  Dram hole exists on this Node's DCTs. */
 	u32 DCTSysLimit;	/* LIMIT[39:8] (system address) of this Node's DCTs */
 	u16 PresetmaxFreq;	/* Maximum OEM defined DDR frequency
-		200=200Mhz (DDR400)
-		266=266Mhz (DDR533)
-		333=333Mhz (DDR667)
-		400=400Mhz (DDR800) */
+		200=200MHz (DDR400)
+		266=266MHz (DDR533)
+		333=333MHz (DDR667)
+		400=400MHz (DDR800) */
 	u8 _2Tmode;		/* 1T or 2T CMD mode (slow access mode)
 		1=1T
 		2=2T */
@@ -476,9 +476,9 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u8 WrDatGrossH;
 	u8 DqsRcvEnGrossL;
 	// NOTE: Not used - u8 NodeSpeed		/* Bus Speed (to set Controller)
-		/* 1=200Mhz */
-		/* 2=266Mhz */
-		/* 3=333Mhz */
+		/* 1=200MHz */
+		/* 2=266MHz */
+		/* 3=333MHz */
 	// NOTE: Not used - u8 NodeCASL		/* CAS latency DCT setting
 		/* 0=2.0 */
 		/* 1=3.0 */
@@ -574,10 +574,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 #define NV_MAX_NODES		1	/* Number of Nodes/Sockets (4-bits)*/
 #define NV_MAX_DIMMS		2	/* Number of DIMM slots for the specified Node ID (4-bits)*/
 #define NV_MAX_MEMCLK		3	/* Maximum platform demonstrated Memclock (10-bits)
-					    200=200Mhz (DDR400)
-					    266=266Mhz (DDR533)
-					    333=333Mhz (DDR667)
-					    400=400Mhz (DDR800)*/
+					    200=200MHz (DDR400)
+					    266=266MHz (DDR533)
+					    333=333MHz (DDR667)
+					    400=400MHz (DDR800)*/
 #define NV_ECC_CAP		4	/* Bus ECC capable (1-bits)
 					    0=Platform not capable
 					    1=Platform is capable*/
@@ -599,10 +599,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 					    1=Auto, user limit provided in NV_MemCkVal
 					    2=Manual, user value provided in NV_MemCkVal*/
 #define NV_MemCkVal		11	/* Memory Clock Value (2-bits)
-					    0=200Mhz
-					    1=266Mhz
-					    2=333Mhz
-					    3=400Mhz*/
+					    0=200MHz
+					    1=266MHz
+					    2=333MHz
+					    3=400MHz*/
 
 /*Dram Configuration*/
 #define NV_BankIntlv		20	/* Dram Bank (chip-select) Interleaving (1-bits)
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index ab1347a9f8..17fb289268 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -591,8 +591,8 @@ void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat,
 	/* When 400, 533, 667, it will support dimm0/1/2/3,
 	 * and set conf for dimm0, hw will copy to dimm1/2/3
 	 * set for dimm1, hw will copy to dimm3
-	 * Rev A/B only support DIMM0/1 when 800Mhz and above + 0x100 to next dimm
-	 * Rev C support DIMM0/1/2/3 when 800Mhz and above  + 0x100 to next dimm
+	 * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm
+	 * Rev C support DIMM0/1/2/3 when 800MHz and above  + 0x100 to next dimm
 	 */
 
 	/* FindDQSDatDimmVal_D is not required since we use an array */
@@ -615,8 +615,8 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat,
 	/* When 400, 533, 667, it will support dimm0/1/2/3,
 	 * and set conf for dimm0, hw will copy to dimm1/2/3
 	 * set for dimm1, hw will copy to dimm3
-	 * Rev A/B only support DIMM0/1 when 800Mhz and above + 0x100 to next dimm
-	 * Rev C support DIMM0/1/2/3 when 800Mhz and above  + 0x100 to next dimm
+	 * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm
+	 * Rev C support DIMM0/1/2/3 when 800MHz and above  + 0x100 to next dimm
 	 */
 
 	/* FindDQSDatDimmVal_D is not required since we use an array */
diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c
index 529a7366eb..ab6f9ce0c0 100644
--- a/src/northbridge/amd/amdmct/mct/mctpro_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c
@@ -290,7 +290,7 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct)
 	tmp = pDCTstat->LogicalCPUID;
 	if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
 		Speed = pDCTstat->Speed;
-		/* MemClkFreq = 333MHz or 533Mhz */
+		/* MemClkFreq = 333MHz or 533MHz */
 		if((Speed == 3) || (Speed == 2)) {
 			if(pDCTstat->GangedMode) {
 				ch_start = 0;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 90b7ed33ec..770b663fe9 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -248,7 +248,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
 	 * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry
 	 * 6. All var MTRRs reset to zero
 	 * 7. State of NB_CFG.DisDatMsk set properly on all CPUs
-	 * 8. All CPUs at 2Ghz Speed (unless DQS training is not installed).
+	 * 8. All CPUs at 2GHz Speed (unless DQS training is not installed).
 	 * 9. All cHT links at max Speed/Width (unless DQS training is not installed).
 	 *
 	 *
@@ -258,13 +258,13 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
 	 * j CL(j)       k   F(k)
 	 * --------------------------
 	 * 0 2.0         -   -
-	 * 1 3.0         1   200 Mhz
-	 * 2 4.0         2   266 Mhz
-	 * 3 5.0         3   333 Mhz
-	 * 4 6.0         4   400 Mhz
-	 * 5 7.0         5   533 Mhz
-	 * 6 8.0         6   667 Mhz
-	 * 7 9.0         7   800 Mhz
+	 * 1 3.0         1   200 MHz
+	 * 2 4.0         2   266 MHz
+	 * 3 5.0         3   333 MHz
+	 * 4 6.0         4   400 MHz
+	 * 5 7.0         5   533 MHz
+	 * 6 8.0         6   667 MHz
+	 * 7 9.0         7   800 MHz
 	 */
 	u8 Node, NodesWmem;
 	u32 node_sys_base;
@@ -487,9 +487,9 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 				 * when 400, 533, 667, it will support dimm0/1/2/3,
 				 * and set conf for dimm0, hw will copy to dimm1/2/3
 				 * set for dimm1, hw will copy to dimm3
-				 * Rev A/B only support DIMM0/1 when 800Mhz and above
+				 * Rev A/B only support DIMM0/1 when 800MHz and above
 				 *   + 0x100 to next dimm
-				 * Rev C support DIMM0/1/2/3 when 800Mhz and above
+				 * Rev C support DIMM0/1/2/3 when 800MHz and above
 				 *   + 0x100 to next dimm
 				*/
 				for (DIMM = 0; DIMM < 4; DIMM++) {
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index d2872e439c..42cca2640b 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -35,8 +35,8 @@
 
 #define J_MIN		0		/* j loop constraint. 1=CL 2.0 T*/
 #define J_MAX		5		/* j loop constraint. 5=CL 7.0 T*/
-#define K_MIN		1		/* k loop constraint. 1=200 Mhz*/
-#define K_MAX		5		/* k loop constraint. 5=533 Mhz*/
+#define K_MIN		1		/* k loop constraint. 1=200 MHz*/
+#define K_MAX		5		/* k loop constraint. 5=533 MHz*/
 #define CL_DEF		2		/* Default value for failsafe operation. 2=CL 4.0 T*/
 #define T_DEF		1		/* Default value for failsafe operation. 1=5ns (cycle time)*/
 
@@ -352,11 +352,11 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u8 DATAload[2];		/*Number of ranks loading CH A DATA*/
 		/* Number of ranks loading CH B DATA*/
 	u8 DIMMAutoSpeed;	/*Max valid Mfg. Speed of DIMMs
-		1=200Mhz
-		2=266Mhz
-		3=333Mhz
-		4=400Mhz
-		5=533Mhz*/
+		1=200MHz
+		2=266MHz
+		3=333MHz
+		4=400MHz
+		5=533MHz*/
 	u8 DIMMCASL;		/* Min valid Mfg. CL bitfield
 		0=2.0
 		1=3.0
@@ -372,10 +372,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u16 DIMMTrrd;		/* Minimax Trrd*40 (ns) of DIMMs*/
 	u16 DIMMTwtr;		/* Minimax Twtr*40 (ns) of DIMMs*/
 	u8 Speed;		/* Bus Speed (to set Controller)
-		1=200Mhz
-		2=266Mhz
-		3=333Mhz
-		4=400Mhz */
+		1=200MHz
+		2=266MHz
+		3=333MHz
+		4=400MHz */
 	u8 CASL;		/* CAS latency DCT setting
 		0=2.0
 		1=3.0
@@ -405,10 +405,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u32 DCTHoleBase;	/* If not zero, BASE[39:8] (system address) of dram hole for HW remapping.  Dram hole exists on this Node's DCTs. */
 	u32 DCTSysLimit;	/* LIMIT[39:8] (system address) of this Node's DCTs */
 	u16 PresetmaxFreq;	/* Maximum OEM defined DDR frequency
-		200=200Mhz (DDR400)
-		266=266Mhz (DDR533)
-		333=333Mhz (DDR667)
-		400=400Mhz (DDR800) */
+		200=200MHz (DDR400)
+		266=266MHz (DDR533)
+		333=333MHz (DDR667)
+		400=400MHz (DDR800) */
 	u8 _2Tmode;		/* 1T or 2T CMD mode (slow access mode)
 		1=1T
 		2=2T */
@@ -518,9 +518,9 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u8 WrDatGrossH;
 	u8 DqsRcvEnGrossL;
 	/* NOTE: Not used - u8 NodeSpeed */		/* Bus Speed (to set Controller) */
-		/* 1=200Mhz */
-		/* 2=266Mhz */
-		/* 3=333Mhz */
+		/* 1=200MHz */
+		/* 2=266MHz */
+		/* 3=333MHz */
 	/* NOTE: Not used - u8 NodeCASL	*/	/* CAS latency DCT setting */
 		/* 0=2.0 */
 		/* 1=3.0 */
@@ -635,10 +635,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 #define NV_MAX_NODES		1	/* Number of Nodes/Sockets (4-bits)*/
 #define NV_MAX_DIMMS		2	/* Number of DIMM slots for the specified Node ID (4-bits)*/
 #define NV_MAX_MEMCLK		3	/* Maximum platform demonstrated Memclock (10-bits)
-					    200=200Mhz (DDR400)
-					    266=266Mhz (DDR533)
-					    333=333Mhz (DDR667)
-					    400=400Mhz (DDR800)*/
+					    200=200MHz (DDR400)
+					    266=266MHz (DDR533)
+					    333=333MHz (DDR667)
+					    400=400MHz (DDR800)*/
 #define NV_ECC_CAP		4	/* Bus ECC capable (1-bits)
 					    0=Platform not capable
 					    1=Platform is capable*/
@@ -660,10 +660,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 					    1=Auto, user limit provided in NV_MemCkVal
 					    2=Manual, user value provided in NV_MemCkVal*/
 #define NV_MemCkVal		11	/* Memory Clock Value (2-bits)
-					    0=200Mhz
-					    1=266Mhz
-					    2=333Mhz
-					    3=400Mhz*/
+					    0=200MHz
+					    1=266MHz
+					    2=333MHz
+					    3=400MHz*/
 
 /*Dram Configuration*/
 #define NV_BankIntlv		20	/* Dram Bank (chip-select) Interleaving (1-bits)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 76d01dadb2..d7084ad385 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -668,8 +668,8 @@ static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat,
 	/* When 400, 533, 667, it will support dimm0/1/2/3,
 	 * and set conf for dimm0, hw will copy to dimm1/2/3
 	 * set for dimm1, hw will copy to dimm3
-	 * Rev A/B only support DIMM0/1 when 800Mhz and above + 0x100 to next dimm
-	 * Rev C support DIMM0/1/2/3 when 800Mhz and above  + 0x100 to next dimm
+	 * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm
+	 * Rev C support DIMM0/1/2/3 when 800MHz and above  + 0x100 to next dimm
 	 */
 
 	/* FindDQSDatDimmVal_D is not required since we use an array */
@@ -709,8 +709,8 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat,
 	/* When 400, 533, 667, it will support dimm0/1/2/3,
 	 * and set conf for dimm0, hw will copy to dimm1/2/3
 	 * set for dimm1, hw will copy to dimm3
-	 * Rev A/B only support DIMM0/1 when 800Mhz and above + 0x100 to next dimm
-	 * Rev C support DIMM0/1/2/3 when 800Mhz and above  + 0x100 to next dimm
+	 * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm
+	 * Rev C support DIMM0/1/2/3 when 800MHz and above  + 0x100 to next dimm
 	 */
 
 	/* FindDQSDatDimmVal_D is not required since we use an array */
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index 1446f4ff6b..80557fdf69 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -741,7 +741,7 @@ void procConifg(sMCTStruct *pMCTData,sDCTStruct *pDCTData, u8 dimm, u8 pass)
 				pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5;
 			/* SeedTotalPreScaling = (the total delay value in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization
 			   training) - RegisterDelay. */
-			/* MemClkFreq: 3: 400Mhz; 4: 533Mhz; 5: 667Mhz; 6: 800Mhz */
+			/* MemClkFreq: 3: 400MHz; 4: 533MHz; 5: 667MHz; 6: 800MHz */
 			SeedTotal = (u16) (RegisterDelay + ((((u32) SeedTotal - RegisterDelay) *
 							     freq_tab[MemClkFreq-3]) / 400));
 			Seed_Gross = (SeedTotal & 0x20) != 0 ? 1 : 2;