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authorMyles Watson <mylesgw@gmail.com>2010-04-15 05:19:29 +0000
committerMyles Watson <mylesgw@gmail.com>2010-04-15 05:19:29 +0000
commit075fbe820127c454a6854b87c277a2ca30dee1c2 (patch)
treeabc89718ed34b04febd7d6beae8e57cd54f3f5b0 /src/northbridge/amd/amdmct
parent07ef092ef228b4cc7c85f375c0390acc901b5181 (diff)
Remove a few more warnings from fam10.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct')
-rw-r--r--src/northbridge/amd/amdmct/mct/mct_d.c10
-rw-r--r--src/northbridge/amd/amdmct/mct/mct_d_gcc.h14
-rw-r--r--src/northbridge/amd/amdmct/mct/mct_fd.c2
-rw-r--r--src/northbridge/amd/amdmct/mct/mctardk4.c2
-rw-r--r--src/northbridge/amd/amdmct/wrappers/mcti_d.c54
5 files changed, 41 insertions, 41 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index ec767fa27c..ef7e2af92a 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -177,7 +177,7 @@ static const u8 Table_Comp_Rise_Slew_15x[] = {7, 7, 3, 2, 0xFF};
static const u8 Table_Comp_Fall_Slew_20x[] = {7, 5, 3, 2, 0xFF};
static const u8 Table_Comp_Fall_Slew_15x[] = {7, 7, 5, 3, 0xFF};
-void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
+static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstatA)
{
/*
@@ -3565,7 +3565,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
u8 Node;
u32 i;
struct DCTStatStruc *pDCTstat;
- u16 start, stop;
+ u32 start, stop;
u8 *p;
u16 host_serv1, host_serv2;
@@ -3582,12 +3582,12 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
p = (u8 *) pDCTstat;
start = 0;
- stop = ((u16) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2]);
+ stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]);
for (i = start; i < stop ; i++) {
p[i] = 0;
}
- start = ((u16) &((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]);
+ start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]);
stop = sizeof(struct DCTStatStruc);
for (i = start; i < stop; i++) {
p[i] = 0;
@@ -3617,7 +3617,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
}
-void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat,
+static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 *dqs_pos)
{
// FIXME: Skip for Ax
diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h
index 8cbeef11df..3e36dfe4cc 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h
@@ -150,7 +150,7 @@ static void WriteLNTestPattern(u32 addr_lo, u8 *buf_a, u32 line_num)
}
-u32 read32_fs(u32 addr_lo)
+static u32 read32_fs(u32 addr_lo)
{
u32 value;
__asm__ volatile (
@@ -162,7 +162,7 @@ u32 read32_fs(u32 addr_lo)
}
-u8 read8_fs(u32 addr_lo)
+static u8 read8_fs(u32 addr_lo)
{
u8 byte;
__asm__ volatile (
@@ -312,7 +312,7 @@ static void ReadMaxRdLat1CLTestPattern_D(u32 addr)
}
-void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr)
+static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr)
{
SetUpperFSbase(addr);
@@ -351,7 +351,7 @@ static void FlushMaxRdLatTestPattern_D(u32 addr)
}
-u32 stream_to_int(u8 *p)
+static u32 stream_to_int(u8 const *p)
{
int i;
u32 val;
@@ -369,19 +369,19 @@ u32 stream_to_int(u8 *p)
}
-void oemSet_NB32(u32 addr, u32 val, u8 *valid)
+static void oemSet_NB32(u32 addr, u32 val, u8 *valid)
{
}
-u32 oemGet_NB32(u32 addr, u8 *valid)
+static u32 oemGet_NB32(u32 addr, u8 *valid)
{
*valid = 0;
return 0xffffffff;
}
-u8 oemNodePresent_D(u8 Node, u8 *ret)
+static u8 oemNodePresent_D(u8 Node, u8 *ret)
{
*ret = 0;
return 0;
diff --git a/src/northbridge/amd/amdmct/mct/mct_fd.c b/src/northbridge/amd/amdmct/mct/mct_fd.c
index c54d6ef90b..168d9957d9 100644
--- a/src/northbridge/amd/amdmct/mct/mct_fd.c
+++ b/src/northbridge/amd/amdmct/mct/mct_fd.c
@@ -19,7 +19,7 @@
-u8 amd_FD_support(void)
+static u8 amd_FD_support(void)
{
return 1;
}
diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c
index c18e8e58ba..9cb2856edb 100644
--- a/src/northbridge/amd/amdmct/mct/mctardk4.c
+++ b/src/northbridge/amd/amdmct/mct/mctardk4.c
@@ -104,7 +104,7 @@ static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
u8 *CMDmode)
{
- u8 *p;
+ u8 const *p;
*AddrTmgCTL = 0;
*ODC_CTL = 0;
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 54ee28f8d5..6dfeb214d0 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -19,7 +19,7 @@
/* Call-backs */
#include <delay.h>
-u16 mctGet_NVbits(u8 index)
+static u16 mctGet_NVbits(u8 index)
{
u16 val = 0;
@@ -223,106 +223,106 @@ u16 mctGet_NVbits(u8 index)
}
-void mctHookAfterDIMMpre(void)
+static void mctHookAfterDIMMpre(void)
{
}
-void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
+static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
{
pDCTstat->PresetmaxFreq = 400;
}
-void mctAdjustAutoCycTmg(void)
+static void mctAdjustAutoCycTmg(void)
{
}
-void mctAdjustAutoCycTmg_D(void)
+static void mctAdjustAutoCycTmg_D(void)
{
}
-void mctHookAfterAutoCycTmg(void)
+static void mctHookAfterAutoCycTmg(void)
{
}
-void mctGetCS_ExcludeMap(void)
+static void mctGetCS_ExcludeMap(void)
{
}
-void mctHookAfterAutoCfg(void)
+static void mctHookAfterAutoCfg(void)
{
}
-void mctHookAfterPSCfg(void)
+static void mctHookAfterPSCfg(void)
{
}
-void mctHookAfterHTMap(void)
+static void mctHookAfterHTMap(void)
{
}
-void mctHookAfterCPU(void)
+static void mctHookAfterCPU(void)
{
}
-void mctSaveDQSSigTmg_D(void)
+static void mctSaveDQSSigTmg_D(void)
{
}
-void mctGetDQSSigTmg_D(void)
+static void mctGetDQSSigTmg_D(void)
{
}
-void mctHookBeforeECC(void)
+static void mctHookBeforeECC(void)
{
}
-void mctHookAfterECC(void)
+static void mctHookAfterECC(void)
{
}
-void mctInitMemGPIOs_A(void)
+static void mctInitMemGPIOs_A(void)
{
}
-void mctInitMemGPIOs_A_D(void)
+static void mctInitMemGPIOs_A_D(void)
{
}
-void mctNodeIDDebugPort_D(void)
+static void mctNodeIDDebugPort_D(void)
{
}
-void mctWarmReset(void)
+static void mctWarmReset(void)
{
}
-void mctWarmReset_D(void)
+static void mctWarmReset_D(void)
{
}
-void mctHookBeforeDramInit(void)
+static void mctHookBeforeDramInit(void)
{
}
-void mctHookAfterDramInit(void)
+static void mctHookAfterDramInit(void)
{
}
@@ -330,7 +330,7 @@ static void coreDelay (void);
/* Erratum 350 */
-void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
+static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
{
u8 u8Channel;
u8 u8Receiver;
@@ -392,23 +392,23 @@ void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
}
-void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
+static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
{
if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2)) {
vErrata350(pMCTstat, pDCTstatA);
}
}
-void mctHookAfterAnyTraining(void)
+static void mctHookAfterAnyTraining(void)
{
}
-u32 mctGetLogicalCPUID_D(u8 node)
+static u32 mctGetLogicalCPUID_D(u8 node)
{
return mctGetLogicalCPUID(node);
}
-u8 mctSetNodeBoundary_D(void)
+static u8 mctSetNodeBoundary_D(void)
{
return 0;
}