diff options
author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/northbridge/amd/amdmct/mct_ddr3 | |
parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 6 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 6f09b12a8a..9178c782d4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2620,7 +2620,7 @@ restartinit: mct_ForceNBPState0_En_Fam15(pMCTstat, pDCTstat); } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n"); if (restore_mct_information_from_nvram(0) != 0) printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); @@ -2692,11 +2692,11 @@ restartinit: nvram = 0; set_option("allow_spd_nvram_cache_restore", &nvram); -#if IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT) +#if CONFIG(DIMM_VOLTAGE_SET_SUPPORT) printk(BIOS_DEBUG, "%s: DIMMSetVoltage\n", __func__); DIMMSetVoltages(pMCTstat, pDCTstatA); /* Set the DIMM voltages (mainboard specific) */ #endif - if (!IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT)) { + if (!CONFIG(DIMM_VOLTAGE_SET_SUPPORT)) { /* Assume 1.5V operation */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; @@ -3674,7 +3674,7 @@ retry_dqs_training_and_levelization: mct_WriteLevelization_HW(pMCTstat, pDCTstatA, SecondPass); -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DIMM training configuration from NVRAM\n"); if (restore_mct_information_from_nvram(1) != 0) printk(BIOS_CRIT, "%s: ERROR: Unable to restore DCT configuration from NVRAM\n", __func__); @@ -5836,7 +5836,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, } } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) calculate_and_store_spd_hashes(pMCTstat, pDCTstat); if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { @@ -5853,7 +5853,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, if (get_option(&nvram, "allow_spd_nvram_cache_restore") == CB_SUCCESS) allow_config_restore = !!nvram; -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#if CONFIG(HAVE_ACPI_RESUME) if (pMCTstat->nvram_checksum != calculate_nvram_mct_hash()) allow_config_restore = 0; #else diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 7267f12000..a78a752052 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -536,7 +536,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_da data->f2x9cx0d0f812f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f812f); /* Stage 11 */ - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (i = 0; i < 12; i++) data->f2x9cx30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x30 + i); for (i = 0; i < 12; i++) @@ -654,7 +654,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]); - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (i = 0; i < 12; i++) write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]); for (i = 0; i < 12; i++) @@ -1093,7 +1093,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste } /* Stage 11 */ - if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + if (CONFIG(DIMM_DDR3)) { for (node = 0; node < MAX_NODES_SUPPORTED; node++) { for (channel = 0; channel < 2; channel++) { struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel]; |