diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-10-16 13:51:51 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-02 23:45:19 +0100 |
| commit | 730a043fb6cb4dd3cb5af8f8640365727b598648 (patch) | |
| tree | 59afe45caca1a8e1682939c7e44e95344104533e /src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c | |
| parent | d150006c4a4584bc9933c2d8ff580a54c4f0cc2a (diff) | |
cpu/amd: Add initial AMD Family 15h support
TEST: Booted ASUS KGPE-D16 with single Opteron 6380
* Unbuffered DDR3 DIMMs tested and working
* Suspend to RAM (S3) tested and working
Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c | 69 |
1 files changed, 59 insertions, 10 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c index 4ae0af183b..18cad7eae7 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -130,24 +131,48 @@ static u32 get_Bits(sDCTStruct *pDCTData, u16 offset, u8 low, u8 high) { u32 temp; + uint32_t dword; + /* ASSERT(node < MAX_NODES); */ if (dct == BOTH_DCTS) { /* Registers exist on DCT0 only */ + if (is_fam15h()) + { + /* Select DCT 0 */ + AmdMemPCIRead(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); + dword &= ~0x1; + AmdMemPCIWrite(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); + } + AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); } else { - if (dct == 1) + if (is_fam15h()) { - /* Write to dct 1 */ - offset += 0x100; + /* Select DCT */ + AmdMemPCIRead(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); + dword &= ~0x1; + dword |= (dct & 0x1); + AmdMemPCIWrite(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); + + /* Read from the selected DCT */ AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); } else { - /* Write to dct 0 */ - AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); + if (dct == 1) + { + /* Read from dct 1 */ + offset += 0x100; + AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); + } + else + { + /* Read from dct 0 */ + AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); + } } } return temp; @@ -180,25 +205,49 @@ static void set_Bits(sDCTStruct *pDCTData, u16 offset, u8 low, u8 high, u32 value) { u32 temp; + uint32_t dword; + temp = value; if (dct == BOTH_DCTS) { /* Registers exist on DCT0 only */ + if (is_fam15h()) + { + /* Select DCT 0 */ + AmdMemPCIRead(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); + dword &= ~0x1; + AmdMemPCIWrite(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); + } + AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); } else { - if (dct == 1) + if (is_fam15h()) { - /* Write to dct 1 */ - offset += 0x100; + /* Select DCT */ + AmdMemPCIRead(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); + dword &= ~0x1; + dword |= (dct & 0x1); + AmdMemPCIWrite(MAKE_SBDFO(0,0,24+node,1,0x10c), &dword); + + /* Write to the selected DCT */ AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); } else { - /* Write to dct 0 */ - AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); + if (dct == 1) + { + /* Write to dct 1 */ + offset += 0x100; + AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); + } + else + { + /* Write to dct 0 */ + AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+node,func,offset), high, low, &temp); + } } } } |