DDR3 support for AMD Fam10.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 39 insertions, 0 deletions

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c
new file mode 100644
index 0000000000..a1132ff7bb
--- /dev/null
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void AmdMemPCIRead(SBDFO loc, u32 *Value)
+{
+	/* Convert SBDFO into a CF8 Address */
+	loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16) ;
+	loc |= 0x80000000;
+
+	outl(loc, 0xCF8);
+
+	*Value = inl(0xCFC);
+}
+
+static void AmdMemPCIWrite(SBDFO loc, u32 *Value)
+{
+	/* Convert SBDFO into a CF8 Address */
+	loc = (loc >> 4 & 0xFFFFFF00) | (loc & 0xFF) | ((loc & 0xF00) << 16) ;
+	loc |= 0x80000000;
+
+	outl(loc, 0xCF8);
+	outl(*Value, 0xCFC);
+}