diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-07-25 01:23:17 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-16 17:31:48 +0100 |
| commit | dc4cb05763fa029d7495f7aa37194f3ee5abaf05 (patch) | |
| tree | 618b990234696615433d6f3618ccb9d8f3a2ccd9 /src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c | |
| parent | 323a2af8e25ad2ff9b81b58f5fccd4ea7d39e72f (diff) | |
nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slots
The current code did not define the number of DIMM slots on the
mainboard, which lead to incorrect configuration values and
occassional training failure.
Add preliminary support for DIMM slot count configuration.
Change-Id: I488511d6262ffa8207c442d133314aed0f75acfb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12016
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c index 427f72408b..8ed03a0454 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -53,7 +54,7 @@ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 d u32 tempW1; tempW1 = 0; if (wl) { - switch (pMCTData->PlatMaxDimmsDct) { + switch (mctGet_NVbits(NV_MAX_DIMMS_PER_CH)) { case 2: /* 2 dimms per channel */ if (pDCTData->MaxDimmsInstalled == 1) { @@ -107,7 +108,7 @@ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 d ASSERT (FALSE); } } else { - switch (pMCTData->PlatMaxDimmsDct) { + switch (mctGet_NVbits(NV_MAX_DIMMS_PER_CH)) { case 2: /* 2 dimms per channel */ if ((pDCTData->DimmRanks[dimm] == 4) && (rank == 1)) { @@ -163,7 +164,7 @@ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 d */ static u32 RttNomNonTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) { - if ((wl) && (pMCTData->PlatMaxDimmsDct == 2) && (pDCTData->DimmRanks[dimm] == 2) && (rank == 1)) { + if ((wl) && (mctGet_NVbits(NV_MAX_DIMMS_PER_CH) == 2) && (pDCTData->DimmRanks[dimm] == 2) && (rank == 1)) { return 0x00; /* for non-target dimm during WL, the second rank of a DR dimm need to have Rtt_Nom = OFF */ } else { return RttNomTargetRegDimm (pMCTData, pDCTData, dimm, FALSE, MemClkFreq, rank); /* otherwise, the same as target dimm in normal mode. */ @@ -193,7 +194,7 @@ static u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BO if (wl) { tempW1 = 0x00; /* Rtt_WR = OFF */ } else { - switch (pMCTData->PlatMaxDimmsDct) { + switch (mctGet_NVbits(NV_MAX_DIMMS_PER_CH)) { case 2: if (pDCTData->MaxDimmsInstalled == 1) { if (pDCTData->DimmRanks[dimm] != 4) { @@ -258,7 +259,7 @@ static u8 WrLvOdtRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm) } i += 2; } - if (pMCTData->PlatMaxDimmsDct == 2) { + if (mctGet_NVbits(NV_MAX_DIMMS_PER_CH) == 2) { if ((pDCTData->DimmRanks[dimm] == 4) && (pDCTData->MaxDimmsInstalled != 1)) { if (dimm >= 2) { WrLvOdt1 = (u8)bitTestReset (WrLvOdt1, (dimm - 2)); |