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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-21 01:08:01 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-04-22 17:29:01 +0200 |
| commit | b474afdd2118baa6e132f8c756d74cb3be6df071 (patch) | |
| tree | 4a16869433f7d02056ad8f85f93d5b821adbc173 /src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | |
| parent | 0b6ff7834238a18258028faa686ef15162ea5d36 (diff) | |
nb/amd/mct_ddr3: Run fence training on each node after memory clock change
The BKDG requires phy fences to be re-trained after a memory clock change.
Memory training on the ASUS KGPE-D16 and KCMA-D8 somehow "mostly" worked
-- without actually following this requirement -- !
Fix the single typo that caused several weeks of delay in putting
servers with Kingston RAM (and others) into production...
Tested-On: ASUS KGPE-D16
Config-CPU: 1x Opteron 6262HE
Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
Change-Id: I197e6728d2b0ac8c1535740599459d080b17af33
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14445
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c')
0 files changed, 0 insertions, 0 deletions