diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-07-28 15:16:46 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-16 18:04:59 +0100 |
| commit | 29016ea3b4350d8c9ed5fad8dff7707ecbb21127 (patch) | |
| tree | 86e3d67b447c903d58b6a53fb539101672f01b1a /src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | |
| parent | f682d0028cb33fc4a085af83344f4a7b9c0e78f2 (diff) | |
northbridge/amd/mct_ddr3: Add registered and x4 DIMM support to Fam15h
The existing MCT support code did not perform any of the requisite
configuration to support registered or x4 DIMMs. Add the needed
configuration per the BKDG for Family 15h.
Change-Id: I9ee0bb7346aa35f564fe535cdd337ec7f6148f2b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12019
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctwl.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index e163227949..4bfcc401ff 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -15,7 +15,7 @@ */ static void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat); + struct DCTStatStruc *pDCTstat, uint8_t dct); static void AgesaDelay(u32 msec) @@ -349,11 +349,14 @@ static void ExitSelfRefresh(struct MCTStatStruc *pMCTstat, } void SetTargetFreq(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat) + struct DCTStatStruc *pDCTstatA, uint8_t Node) { uint32_t dword; uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (is_fam15h()) { /* Program F2x[1, 0]90[DisDllShutDownSR]=1. */ if (pDCTstat->DIMMValidDCT[0]) { @@ -387,7 +390,7 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, uint8_t dct; for (dct = 0; dct < 2; dct++) { if (pDCTstat->DIMMValidDCT[dct]) { - phyAssistedMemFnceTraining(pMCTstat, pDCTstat); + phyAssistedMemFnceTraining(pMCTstat, pDCTstatA, Node); InitPhyCompensation(pMCTstat, pDCTstat, dct); } } @@ -434,7 +437,12 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat, else pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[1]; - FreqChgCtrlWrd(pMCTstat, pDCTstat); + if (pDCTstat->DIMMValidDCT[0]) { + FreqChgCtrlWrd(pMCTstat, pDCTstat, 0); + } + if (pDCTstat->DIMMValidDCT[1]) { + FreqChgCtrlWrd(pMCTstat, pDCTstat, 1); + } } } |