diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-03-21 13:22:37 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-03-24 22:24:11 +0100 |
| commit | 54accfe0d6a693299c5f79f254c30d9ba68c38fa (patch) | |
| tree | 6121f75a22bec7730cb2e4622164b75407c6be0d /src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | |
| parent | 1fc02d1d34320c52525b2c004f587529c04caeb2 (diff) | |
nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
During maximum read latency training on Family 15h processors,
the maximum read latency was incorrectly set from the NBP1
value instead of the correct NBP0 value.
Modify maximimum read latency training to explicitly operate
on the NBP0 value, and store the previously calculated NBP1
value for reference by other portions of the training algorithm.
Change-Id: I5d4a6c2def83df3e23f1a4c598314c31a0172cd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14150
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index 1b18efa259..8cda2f8db0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -191,7 +191,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u8 ChannelDTD; printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n"); for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) { - printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]); + printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]); } } #endif @@ -208,9 +208,9 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat, if (pDCTstat->GangedMode) { Channel = 0; /* for safe */ for (i=0; i<2; i++) - pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal; + pDCTstat->CH_MaxRdLat[i][0] = MaxRdLatVal; } else { - pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal; + pDCTstat->CH_MaxRdLat[Channel][0] = MaxRdLatVal; } dev = pDCTstat->dev_dct; |