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authorArthur Heymans <arthur@aheymans.xyz>2019-11-19 15:46:49 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-20 19:08:30 +0000
commitffcac3eb502bbe0acbb30d6fe804f00e07461a7a (patch)
treed5deda572bb252a683a5ece24a5c4916ee198836 /src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c
parent1ca978ee6529251ed80b47da679be7adc75fa46a (diff)
nb/amd/fam10: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: If36ef0749dbb661f731fb04829bd7e2202ebb422 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c104
1 files changed, 0 insertions, 104 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c
deleted file mode 100644
index 98aadddc6c..0000000000
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cpu.h>
-#include <stdint.h>
-
-#include "mct_d.h"
-#include "mct_d_gcc.h"
-
-static uint8_t is_fam15h(void)
-{
- uint8_t fam15h = 0;
- uint32_t family;
-
- family = cpuid_eax(0x80000001);
- family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
-
- if (family >= 0x6f)
- /* Family 15h or later */
- fam15h = 1;
-
- return fam15h;
-}
-
-u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass)
-{
- u8 ret = 1;
-
- if (is_fam15h()) {
- /* Fam15h needs two passes */
- ret = 1;
- } else {
- if (pass == SecondPass)
- ret = 0;
- }
-
- return ret;
-}
-
-u32 SetupDqsPattern_1PassA(u8 pass)
-{
- return (u32) TestPattern1_D;
-}
-
-u32 SetupDqsPattern_1PassB(u8 pass)
-{
- return (u32) TestPattern0_D;
-}
-
-static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 Receiver,
- u8 Pass)
-{
- u16 i, MaxValue;
- u16 *p;
- u16 val;
-
- MaxValue = 0;
- p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1];
-
- for (i = 0; i < 8; i++) {
- /* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/
- val = p[i];
- /* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/
- val += Pass1MemClkDly;
- /* write back the value to stack */
- if (val > MaxValue)
- MaxValue = val;
-
- p[i] = val;
- }
- /* pDCTstat->DimmTrainFail &= ~(1<<Receiver+Channel); */
-
- return MaxValue;
-}
-
-u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass)
-{
- u8 ret;
- ret = 0;
- if ((pDCTstat->DqsRcvEn_Pass == 0xff) && (pass== FirstPass))
- ret = 2;
- return ret;
-}
-
-u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
- u16 RcvrEnDly, u16 RcvrEnDlyLimit,
- u8 Channel, u8 Receiver, u8 Pass)
-
-{
- return mct_Average_RcvrEnDly_1Pass(pDCTstat, Channel, Receiver, Pass);
-}