diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-27 17:52:45 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-11-15 02:45:37 +0100 |
| commit | a44daac7e6b7b4794f8346c9ae1e998e4f692e83 (patch) | |
| tree | 6336ff1014e7660e69cf0dd306d347a4b2a8b5b8 /src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | |
| parent | 4ef4fc6c3bc9bb65d9336c9b695ed53a05fe0151 (diff) | |
northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failure
In the course of adding full Family 15h MCT support some Family
15h specific settings were inadvertently applied to Family 10h
processors.
Only apply Family15h specific settings to Family 15h processors.
Change-Id: I5dcb333d3a5a49318fe7bddd4c386642205c343e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12013
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 4397ebaccb..38991c813f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -904,9 +904,15 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, * Flush the receiver FIFO * Write one full cache line of non-0x55/0xaa data to one of the test addresses, then read it back to flush the FIFO */ - + /* FIXME + * This does not seem to be needed, and has a tendency to lock up the + * boot process while attempting to write the test pattern. + */ +#if 0 + SetUpperFSbase(TestAddr0); WriteLNTestPattern(TestAddr0 << 8, (uint8_t *)TestPattern2_D, 1); mct_Read1LTestPattern_D(pMCTstat, pDCTstat, TestAddr0); +#endif } MaxDelay_CH[Channel] = CTLRMaxDelay; } |