amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h

Sufficient support has been added to allow booting with registered
DIMMs on the KGPE-D16 in certain slots.  ECC support needs additional
work; the ECC data lanes appear to cause boot failures in some slots.

Change-Id: Ieaf4cbf351908e5a89760be49a6667dc55dbc575
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12017
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
index 7b7b225aa0..718a61fac7 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
@@ -492,6 +492,8 @@ static u32 mct_MR2(struct MCTStatStruc *pMCTstat,
 		ret |= ((dword >> 10) & 3) << 9;
 	}
 
+	printk(BIOS_SPEW, "Going to send MR2 control word %08x\n", ret);
+
 	return ret;
 }
 
@@ -521,6 +523,8 @@ static u32 mct_MR3(struct MCTStatStruc *pMCTstat,
 		ret |= (dword >> 24) & 7;
 	}
 
+	printk(BIOS_SPEW, "Going to send MR3 control word %08x\n", ret);
+
 	return ret;
 }
 
@@ -615,6 +619,8 @@ static u32 mct_MR1(struct MCTStatStruc *pMCTstat,
 			ret |= 1 << 12;
 	}
 
+	printk(BIOS_SPEW, "Going to send MR1 control word %08x\n", ret);
+
 	return ret;
 }
 
@@ -734,6 +740,8 @@ static u32 mct_MR0(struct MCTStatStruc *pMCTstat,
 		ret |= 1 << 8;
 	}
 
+	printk(BIOS_SPEW, "Going to send MR0 control word %08x\n", ret);
+
 	return ret;
 }