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authorZheng Bao <zheng.bao@amd.com>2011-01-06 02:18:12 +0000
committerZheng Bao <Zheng.Bao@amd.com>2011-01-06 02:18:12 +0000
commit69436e1a8ccf50d67004f74360f3ff5e6a146b9a (patch)
treea1765936b1304bcc16aaba9dafe7ead509cf50ec /src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
parentda712f3f45bf27dc7326887c2d38cc7599f7448a (diff)
Fix some settings fo AMD MCT. It is based on BIOS test suite.
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
index 18ef4770e2..3318896fe4 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
@@ -158,7 +158,7 @@ static u32 mct_MR1(struct MCTStatStruc *pMCTstat,
if (dword & (1 << 7))
ret |= 1 << 2;
} else {
- /* TODO: mct_MR1Odt_RDimm */
+ ret |= mct_MR1Odt_RDimm(pMCTstat, pDCTstat, dct, MrsChipSel);
}
/* program MrsAddress[11]=TDQS: based on F2x[1,0]94[RDqsEn] */