diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-27 23:37:38 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-01 16:31:02 +0100 |
| commit | 5edc6695f8fb129a89a80af592b8b3342377a871 (patch) | |
| tree | e8f0190406a76578a4f455e206c2f2d40b672538 /src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | |
| parent | d45a3477b79df14ed13a64e580a26380ebfb2565 (diff) | |
nb/amd/mct_ddr3: Add Family 15h tristate enable codes
The Family 15h DRAM initialization did not set up the various
tristate enable codes in the MCT.
Add Family 15h tristate enable setup. This fixes multiple
DIMMs on a single channel.
Change-Id: I0278656e98461882d0a64519dfde54a6cf28ab0f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12060
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index c1bb89e978..143290f4be 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -841,6 +841,10 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, */ } + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[dct]; + if (pDCTstat->GangedMode & 1) + pDCTstat->CSPresent = pDCTstat->CSPresent_DCT[0]; + /* The following steps are performed once for unbuffered DIMMs and once for each * chip select on registered DIMMs: */ for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel++) { |