diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-19 10:25:41 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-21 16:49:15 +0200 |
| commit | e1606731b63bedd12398acb57a115aa5d280811e (patch) | |
| tree | 8da66e35adfc3142ae1eb822899abf039c975432 /src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | |
| parent | 8aa20193a6dc12ba6cf740b1ad41023475d69698 (diff) | |
northbridge/amd/amdmct: Improve code formatting
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctrci.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c index 951a71265e..ac24c6d8cc 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c @@ -336,14 +336,14 @@ void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat, printk(BIOS_SPEW, "%s: F2xA8: %08x\n", __func__, val); if (is_fam15h()) { - for (cw=0; cw <=15; cw ++) { + for (cw = 0; cw <=15; cw ++) { val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw); mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); if ((cw == 2) || (cw == 8) || (cw == 10)) precise_ndelay_fam15(pMCTstat, 6000); } } else { - for (cw=0; cw <=15; cw ++) { + for (cw = 0; cw <=15; cw ++) { mct_Wait(1600); val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw); mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val); |