diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-24 19:15:09 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-11-15 02:43:22 +0100 |
| commit | eb2f6fff3265b5be87e2dfc9e69ad465c742ec8c (patch) | |
| tree | e4416a4bad6419eea3e8415b35c82a16fc304cbf /src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | |
| parent | 876bdd4ab3591079d3ffa5b9b0fb6080098ea769 (diff) | |
northbridge/amd/amdmct/mct_ddr3: Fix lockups and wasted time during ECC init
The existing ECC initialization algorithm contained several bugs on both
Family 10h and Family 15h processors, including activation of ECC scrub
before DRAM setup was completed, in violation of both BKDG and errata
recommendations.
Change-Id: I09a8ea83024186b7ece7d78a4bef1201ab34ff8a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12002
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctproc.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c index a86c319a88..77acaec3a4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c @@ -19,7 +19,27 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, u8 dct, u32 misc2) { u32 val; - if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { + /* FIXME + * Mainboards need to be able to specify the maximum number of DIMMs installable per channel + * For now assume a maximum of 2 DIMMs per channel can be installed + */ + uint8_t MaxDimmsInstallable = 2; + + if (pDCTstat->LogicalCPUID & AMD_FAM15_ALL) { + uint8_t cs_mux_45; + uint8_t cs_mux_67; + + /* BKDG v3.14 Table 200 / Table 201 */ + if (MaxDimmsInstallable < 3) { + cs_mux_45 = 1; + cs_mux_67 = 1; + } else { + cs_mux_45 = 0; + cs_mux_67 = 0; + } + misc2 |= (cs_mux_45 & 0x1) << 26; + misc2 |= (cs_mux_67 & 0x1) << 27; + } else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { if (pDCTstat->Status & (1 << SB_Registered)) { misc2 |= 1 << SubMemclkRegDly; if (mctGet_NVbits(NV_MAX_DIMMS) == 8) |