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authorZheng Bao <zheng.bao@amd.com>2010-04-23 17:32:48 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-23 17:32:48 +0000
commiteb75f652d392d2f4f257194e112f3f0db7479145 (patch)
treeaa972907734abcba4ca52f2a3a71f8d81d4bdce0 /src/northbridge/amd/amdmct/mct_ddr3/mctprob.c
parentfe6c2cda6e6977894d9b668af9509b983c850f68 (diff)
DDR3 support for AMD Fam10.
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctprob.c')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctprob.c37
1 files changed, 37 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c b/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c
new file mode 100644
index 0000000000..cfd4adfa6f
--- /dev/null
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctprob.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+void mct_BeforeDQSTrainSamp(struct DCTStatStruc *pDCTstat)
+{
+ u32 val;
+
+ if (pDCTstat->LogicalCPUID & AMD_DR_Bx) {
+ Set_NB32(pDCTstat->dev_dct, 0x98, 0x0D004007);
+ val = Get_NB32(pDCTstat->dev_dct, 0x9C);
+ val |= 0x3FF;
+ Set_NB32(pDCTstat->dev_dct, 0x9C, val);
+ Set_NB32(pDCTstat->dev_dct, 0x98, 0x4D0F4F07);
+
+ Set_NB32(pDCTstat->dev_dct, 0x198, 0x0D004007);
+ val = Get_NB32(pDCTstat->dev_dct, 0x19C);
+ val |= 0x3FF;
+ Set_NB32(pDCTstat->dev_dct, 0x19C, val);
+ Set_NB32(pDCTstat->dev_dct, 0x198, 0x4D0F4F07);
+ }
+}