northbridge/amd: Add required space before opening parenthesis '('

Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 11 insertions, 11 deletions

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
index b7c0476e57..8ed2befb34 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
@@ -43,15 +43,15 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
 	 */
 
 	val = mctGet_NVbits(NV_BottomIO);
-	if(val == 0)
+	if (val == 0)
 		val++;
 
 	Bottom32bIO = val << (24-8);
 
 	val = pMCTstat->SysLimit + 1;
-	if(val <= _4GB_RJ8) {
+	if (val <= _4GB_RJ8) {
 		Bottom40bIO = 0;
-		if(Bottom32bIO >= val)
+		if (Bottom32bIO >= val)
 			Bottom32bIO = val;
 	} else {
 		Bottom40bIO = val;
@@ -89,7 +89,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
 				/* Base */
 				/* Limit */
 				/* MtrrAddr */
-	if(addr == -1)		/* ran out of MTRRs?*/
+	if (addr == -1)		/* ran out of MTRRs?*/
 		pMCTstat->GStatus |= 1<<GSB_MTRRshort;
 
 	pMCTstat->Sub4GCacheTop = Cache32bTOP<<8;
@@ -103,7 +103,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
 	_WRMSR(addr, lo, hi);
 	printk(BIOS_DEBUG, "\t CPUMemTyping: Bottom32bIO:%x\n", Bottom32bIO);
 	printk(BIOS_DEBUG, "\t CPUMemTyping: Bottom40bIO:%x\n", Bottom40bIO);
-	if(Bottom40bIO) {
+	if (Bottom40bIO) {
 		hi = Bottom40bIO >> 24;
 		lo = Bottom40bIO << 8;
 		addr += 3;		/* TOM2 */
@@ -111,7 +111,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
 	}
 	addr = 0xC0010010;		/* SYS_CFG */
 	_RDMSR(addr, &lo, &hi);
-	if(Bottom40bIO) {
+	if (Bottom40bIO) {
 		lo |= (1<<21);		/* MtrrTom2En=1 */
 		lo |= (1<<22);		/* Tom2ForceMemTypeWB */
 	} else {
@@ -158,7 +158,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType)
 	val = curBase = Base;
 	curLimit = *pLimit;
 	addr = *pMtrrAddr;
-	while((addr >= 0x200) && (addr < 0x20C) && (val < *pLimit)) {
+	while ((addr >= 0x200) && (addr < 0x20C) && (val < *pLimit)) {
 		/* start with "ascending" code path */
 		/* alignment (largest block size)*/
 		valx = 1 << bsf(curBase);
@@ -166,7 +166,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType)
 
 		/* largest legal limit, given current non-zero range Base*/
 		valx += curBase;
-		if((curBase == 0) || (*pLimit < valx)) {
+		if ((curBase == 0) || (*pLimit < valx)) {
 			/* flop direction to "descending" code path*/
 			valx = 1<<bsr(*pLimit - curBase);
 			curSize = valx;
@@ -189,7 +189,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType)
 		curBase = val;			/* next Base = current Limit (loop exit)*/
 		addr++;				/* next MTRR pair addr */
 	}
-	if(val < *pLimit) {
+	if (val < *pLimit) {
 		*pLimit = val;
 		addr = -1;
 	}
@@ -234,7 +234,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat
 		addr = 0x200;
 		lo = 0;
 		hi = lo;
-		while( addr < 0x20C) {
+		while ( addr < 0x20C) {
 			_WRMSR(addr, lo, hi);		/* prog. MTRR with current region Mask */
 			addr++;						/* next MTRR pair addr */
 		}
@@ -244,7 +244,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat
 		 *======================================================================*/
 		printk(BIOS_DEBUG, "\t UMAMemTyping_D: Cache32bTOP:%x\n", Cache32bTOP);
 		SetMTRRrangeWB_D(0, &Cache32bTOP, &addr);
-		if(addr == -1)		/* ran out of MTRRs?*/
+		if (addr == -1)		/* ran out of MTRRs?*/
 			pMCTstat->GStatus |= 1<<GSB_MTRRshort;
 	}
 }