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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-04-06 22:07:58 -0500
committerTimothy Pearson <tpearson@raptorengineeringinc.com>2016-04-08 17:21:09 +0200
commitba817d0931eb9bbf23d6c09f56f9ea2ba22fdad6 (patch)
tree0b0e0e086ba403de436a1f897aae9871bdc33d11 /src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
parente9205d537ca92e0dfa882a76617e8e9fb664e108 (diff)
nb/amd/mct_ddr3: Reenable sync flood after ECC init
The sync flood reset fix in Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248 and related changes have made it possible to move the sync flood enable statements back into romstage. Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebece Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14270 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 65de0f8c6a..203d11273d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -264,6 +264,15 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
/* Clear MC4 error status */
pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0);
pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0);
+
+ /* Restore MCA settings */
+ if (pDCTstat->mca_config_backed_up) {
+ val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44);
+ val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30;
+ val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21;
+ val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2;
+ pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val);
+ }
}
}
}