diff options
| author | Marc Jones <marc.jones@se-eng.com> | 2012-02-21 17:06:40 -0700 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-03-02 23:35:26 +0100 |
| commit | 067d22340c68d21f0dd5a33cf02701bc54005a0d (patch) | |
| tree | 36c9dab29b3ef4884dcc9b0d356c70714f1036c5 /src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | |
| parent | 07408e687ce440bf665cd6d04d65075b20db0215 (diff) | |
Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
The logic was backwards on the ECC enable/disable option. Also added better
debug output when the debug RAM init feature is enabled.
Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/670
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index ca03f4b5ac..6107e80d25 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -127,7 +127,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -146,6 +146,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) Set_NB32(dev, reg, val); DCTMemClr_Init_D(pMCTstat, pDCTstat); MemClrECC = 1; + printk(BIOS_DEBUG, " ECC enabled on node: %02x\n", Node); } } /* this node has ECC enabled dram */ } else { @@ -207,6 +208,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + printk(BIOS_DEBUG, "ECCInit: Node %02x\n", Node); + printk(BIOS_DEBUG, "ECCInit: Status %x\n", pDCTstat->Status); + printk(BIOS_DEBUG, "ECCInit: ErrStatus %x\n", pDCTstat->ErrStatus); + printk(BIOS_DEBUG, "ECCInit: ErrCode %x\n", pDCTstat->ErrCode); + printk(BIOS_DEBUG, "ECCInit: Done\n"); + } + } return MemClrECC; } |