diff options
| author | Zheng Bao <zheng.bao@amd.com> | 2011-01-06 02:18:12 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2011-01-06 02:18:12 +0000 |
| commit | 69436e1a8ccf50d67004f74360f3ff5e6a146b9a (patch) | |
| tree | a1765936b1304bcc16aaba9dafe7ead509cf50ec /src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | |
| parent | da712f3f45bf27dc7326887c2d38cc7599f7448a (diff) | |
Fix some settings fo AMD MCT. It is based on BIOS test suite.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index c89a32528e..54fdedf08c 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -552,6 +552,18 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat, } if (BanksPresent) { + #if 0 /* show the bitmap */ + for (ByteLane = 0; ByteLane < 8; ByteLane++) { /* just print ByteLane 0 */ + for (DQSDelay = 0; DQSDelay < dqsDelay_end; DQSDelay++) { + if (!(MutualCSPassW[DQSDelay] &(1 << ByteLane))) { + printk(BIOS_DEBUG, "."); + } else { + printk(BIOS_DEBUG, "*"); + } + } + printk(BIOS_DEBUG, "\n"); + } + #endif for (ByteLane = 0; ByteLane < 8; ByteLane++) { print_debug_dqs("\t\t\t\tTrainDQSPos: 31 ByteLane ",ByteLane, 4); if (!(pDCTstat->DqsRdWrPos_Saved &(1 << ByteLane))) { |