diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-10-16 13:51:51 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-02 23:45:19 +0100 |
| commit | 730a043fb6cb4dd3cb5af8f8640365727b598648 (patch) | |
| tree | 59afe45caca1a8e1682939c7e44e95344104533e /src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c | |
| parent | d150006c4a4584bc9933c2d8ff580a54c4f0cc2a (diff) | |
cpu/amd: Add initial AMD Family 15h support
TEST: Booted ASUS KGPE-D16 with single Opteron 6380
* Unbuffered DDR3 DIMMs tested and working
* Suspend to RAM (S3) tested and working
Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c index 94f7716758..253a89fbc0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,7 +32,6 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, u32 dev; u32 reg; - u32 reg_off; u32 val; u32 val_lo, val_hi; @@ -40,16 +40,15 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, EnChipSels = 0; dev = pDCTstat->dev_dct; - reg_off = 0x100 * dct; ChipSel = 0; /* Find out if current configuration is capable */ while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) { - reg = 0x40+(ChipSel<<2) + reg_off; /* Dram CS Base 0 */ - val = Get_NB32(dev, reg); + reg = 0x40+(ChipSel<<2); /* Dram CS Base 0 */ + val = Get_NB32_DCT(dev, dct, reg); if ( val & (1<<CSEnable)) { EnChipSels++; - reg = 0x60+((ChipSel>>1)<<2)+reg_off; /*Dram CS Mask 0 */ - val = Get_NB32(dev, reg); + reg = 0x60+((ChipSel>>1)<<2); /*Dram CS Mask 0 */ + val = Get_NB32_DCT(dev, dct, reg); val >>= 19; val &= 0x3ff; val++; @@ -59,8 +58,8 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, /*If mask sizes not same then skip */ if (val != MemSize) break; - reg = 0x80 + reg_off; /*Dram Bank Addressing */ - val = Get_NB32(dev, reg); + reg = 0x80; /*Dram Bank Addressing */ + val = Get_NB32_DCT(dev, dct, reg); val >>= (ChipSel>>1)<<2; val &= 0x0f; if(EnChipSels == 1) @@ -99,8 +98,8 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, BitDelta = bsf(AddrHiMask) - bsf(AddrLoMask); for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel++) { - reg = 0x40+(ChipSel<<2) + reg_off; /*Dram CS Base 0 */ - val = Get_NB32(dev, reg); + reg = 0x40+(ChipSel<<2); /*Dram CS Base 0 */ + val = Get_NB32_DCT(dev, dct, reg); if (val & 3) { val_lo = val & AddrLoMask; val_hi = val & AddrHiMask; @@ -110,13 +109,13 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, val_hi >>= BitDelta; val |= val_lo; val |= val_hi; - Set_NB32(dev, reg, val); + Set_NB32_DCT(dev, dct, reg, val); if(ChipSel & 1) continue; - reg = 0x60 + ((ChipSel>>1)<<2) + reg_off; /*Dram CS Mask 0 */ - val = Get_NB32(dev, reg); + reg = 0x60 + ((ChipSel>>1)<<2); /*Dram CS Mask 0 */ + val = Get_NB32_DCT(dev, dct, reg); val_lo = val & AddrLoMask; val_hi = val & AddrHiMask; val &= AddrLoMaskN; @@ -125,7 +124,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, val_hi >>= BitDelta; val |= val_lo; val |= val_hi; - Set_NB32(dev, reg, val); + Set_NB32_DCT(dev, dct, reg, val); } } } /* DoIntlv */ |