diff options
author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2010-08-22 19:51:34 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-08-22 19:51:34 +0000 |
commit | 213ab94ea4bd23f4b5f2b00a09a535925fe2c6a6 (patch) | |
tree | d1f98281b2f7d757ab34af119e9929f30f72ef1a /src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | |
parent | e9f0dfe63185222e403d81dd1b6bce27d81eb9a5 (diff) |
documented workaround erratum 372, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
with this one it stops here or earlier (as soon as before the patch,
sometimes):
*** Yes, the copy/decompress is taking a while, FIXME!
v_esp=000cbf48
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region:
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.h')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index bef9dfe954..a30ac7b911 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -175,6 +175,7 @@ #define Ddr3FourSocketCh 2 /* func 2, offset A8h, bit 2 */ #define SendControlWord 30 /* func 2, offset 7Ch, bit 30 */ +#define NB_GfxNbPstateDis 62 /* MSRC001_001F Northbridge Configuration Register (NB_CFG) bit 62 GfxNbPstateDis disable northbridge p-state transitions */ /*============================================================================= SW Initialization ============================================================================*/ |