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author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-05-07 17:26:40 -0500 |
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committer | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-05-09 20:44:11 +0200 |
commit | 84da72c988955c7bdeccf889b1f682582a428752 (patch) | |
tree | f3bf0fa44f57e04b6301ef3d48029703829c2d50 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | |
parent | 251ce85b585b75c90d80b4ae3d0ecd0769afba8a (diff) |
nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure
The existing DIMM size calculation for DDR3 was incorrect. Use
the recommended calculation from the DDR3 SPD specification.
Change-Id: Id6a39e2b38b5d9f483341ebef8f2960ae52bda6c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14739
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.h')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index a5a3d88044..e1d9da53fb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -621,6 +621,8 @@ struct DCTStatStruc { /* A per Node structure*/ uint8_t DimmRanks[MAX_DIMMS_SUPPORTED]; uint8_t DimmBanks[MAX_DIMMS_SUPPORTED]; uint8_t DimmWidth[MAX_DIMMS_SUPPORTED]; + uint64_t DimmChipSize[MAX_DIMMS_SUPPORTED]; + uint32_t DimmChipWidth[MAX_DIMMS_SUPPORTED]; uint8_t DimmRegistered[MAX_DIMMS_SUPPORTED]; uint8_t DimmLoadReduced[MAX_DIMMS_SUPPORTED]; |