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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-08 19:54:56 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-11-11 20:30:45 +0100 |
| commit | 45de61de8bb5ef15a900415a482449cfde019549 (patch) | |
| tree | 8150b83a3ed9be38ac01996a511d17f1297e426e /src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | |
| parent | 83abd81c8acb3a53dfc125e248d9e5fd58f3e0f7 (diff) | |
northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged
Change-Id: I5fee5f5fdf30ab6e3c4f94ed3e54ea66c1204352
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11980
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.h')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 1ac7bbfe62..196d96d083 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -312,6 +312,7 @@ struct MCTStatStruc { #define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/ #define GSB_EnDIMMSpareNW 17 /* Indicates that DIMM Spare can be used without a warm reset */ /* NOTE: This is a local bit used by memory code */ +#define GSB_ConfigRestored 18 /* Training configuration was restored from NVRAM */ /*=============================================================================== Local DCT Status structure (a structure for each DCT) |