diff options
| author | Zheng Bao <zheng.bao@amd.com> | 2010-10-09 02:31:10 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2010-10-09 02:31:10 +0000 |
| commit | 1dcf66896dc90edee0dd8eda4d99618f1bc1dcb8 (patch) | |
| tree | 28462953cfdfc2428d03b36ab6ba9ed54584cd85 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | |
| parent | 713ae2c0906e442bbe9af6d2e3850ca46e5e10b4 (diff) | |
Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.h')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 0de0a0bd42..a7b6697b75 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -263,7 +263,7 @@ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ /*----------------------------- - Jdec DDR II related equates + Jedec DDR II related equates -----------------------------*/ #define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/ #define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/ @@ -464,7 +464,7 @@ struct DCTStatStruc { /* A per Node structure*/ u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/ u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/ u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/ - u16 ChannelTrainFai; /* Bitmap showing the chanel informaiton about failed Chip Selects + u16 ChannelTrainFai; /* Bitmap showing the channel information about failed Chip Selects 0 in any bit field indicates Channel 0 1 in any bit field indicates Channel 1 */ u16 DIMMTfaw; /* Minimax Tfaw*16 (ns) of DIMMs */ @@ -513,7 +513,7 @@ struct DCTStatStruc { /* A per Node structure*/ u8 MaxDCTs; /* Max number of DCTs in system*/ /* NOTE: removed u8 DCT. Use ->dev_ for pci R/W; */ /*DCT pointer*/ u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/ - u8 DRPresent; /* Family 10 present flag, 0 = n0t Fam10, 1 = Fam10*/ + u8 DRPresent; /* Family 10 present flag, 0 = not Fam10, 1 = Fam10*/ u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/ u8 WrDatGrossH; u8 DqsRcvEnGrossL; |