diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-26 14:15:57 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-11-15 02:44:36 +0100 |
| commit | f3aa375f44531ca4a504186d76e69b6d07dc4ae7 (patch) | |
| tree | 211d71c562a131f5bc3c713493d48d8969718017 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | |
| parent | b7a8b8c6fb4a8b76942e1d8d1885c6f817376b65 (diff) | |
northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt values
The existing code did not set Rtt timing parameters when registered
DIMMs were used with Family 15h processors. Set the Rtt values
according to the BKDG recommendations.
Change-Id: I80cd7f8aec12951611d802f33e5e167a41dd532e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12010
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 033f07b808..c3c397677e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -903,8 +903,8 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT } } else if (MaxDimmsInstallable == 3) { /* TODO - * 3 DIMM/channel support unimplemented - */ + * 3 DIMM/channel support unimplemented + */ } } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { /* LRDIMM */ |